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17. Clock & Reset

17.1 Overview​

The K3 SoC integrates multiple on-chip clock sources and reset controls to support a wide range of operational scenarios, providing high flexibility, stability, and power efficiency. K3 comes with the following clocks:

  • One 24M OSC clock
  • One 32K RTC clock

17.2 Features​

  • Eight integrated PLLs providing multiple frequency options for diverse system requirements
  • Dynamic Voltage and Frequency Scaling (DVFS) support for optimal power–performance balance
  • Glitch-free clock switching and programmable clock dividers to efficiently generate required frequencies while minimizing PLL resource cost
  • Fine-grained clock gating and software-controlled reset mechanisms for improved power saving and flexible system management

17.3 Functional Description​

17.3.1 Clock System​

The detailed clock tree structure is depicted below, highlighting how the clock signals are generated, managed, and distributed across the system to support various modules and functions.

Clock Tree Structure in PDF

The K3 SoC integrates eight Phase-Locked Loops (PLLs) designed to provide a wide range of stable and configurable frequency sources for different modules and CPU clusters. Each PLL supports programmable control through the Main PMU registers and is optimized for low jitter and quick lock time.

  • PLL1 PLL1 is designed to generate fixed frequency points for CPU cores and system peripherals.

  • PLL2 PLL2 is designed to generate multiple fixed frequencies that complement PLL1, providing a full range of clock sources for peripheral modules.

  • PLL3 PLL3 provides clock frequencies for CPU Cluster 0/1 frequency scaling and dynamic switching.

  • PLL4 PLL4 provides clock frequencies for CPU Cluster 1 frequency scaling and switching.

  • PLL5 PLL5 provides clock frequencies for CPU Cluster 2/3 frequency scaling and switching.

  • PLL6 PLL6 generates additional fixed frequencies to extend system clock flexibility alongside PLL1.

  • PLL7 PLL7 generates supplementary fixed frequencies to support various system and peripheral modules.

  • PLL8 PLL8 provides clock frequencies for CPU Cluster 3 frequency scaling and dynamic switching.

17.3.2 Resource Reset Schemes​

The K3 SoC supports different resource reset schemes, as listed below.

No.Resource Reset SchemeDescription
1Power-On ResetReset the whole chip during the power-on sequence
2Watchdog ResetReset the whole chip, excluding pinmux registers and debug registers
3Module Software ResetReset each module individually through software
4Power Island POR ResetReset the whole power island during its power-on sequence

17.4 Registers​

17.4.1 Module Base Address​

Clock/Reset regionBase Address
PMUMAIN0xD4050000
APB_SPARE0xD4090000
APBCLOCK0xD4015000
PMUAP0xD4282800
CIUDRAGON0xD8440000
APB2CLOCK0xF0610000
RCPU_SYSCTRL0xC0880000
RCPU_UARTCTRL0xC0881F00
RCPU_I2SCTRL0xC0882000
RCPU_SPICTRL0xC0885F00
RCPU_I2CCTRL0xC0886F00
RCPU_PMU0xC088C000
RCPU_PWMCTRL0xC088D000

17.4.2 Register Description​

PMUMAIN​

FREQUENCY CHANGE CONTROL REGISTER​

FCCR Offset:0x8

BitsFieldTypeResetDescription
31:30RSVDRO0x0Reserved for future use
29I2SCLK307MRW0x0I2S Divider Clock 307M Select (or half)
1 = 307.2 MHz
0 = 307.2 MHz / 2 = 153.6 MHz
28I2SCLKSELRW0x0I2S Divider Clock Selection
1 = From VCTCXO
0 = From 307.2 MHz clock
27:9RSVDRO0x0Reserved for future use
8:0PLL1FBDRW0x0These register bits are not used in Aquila and are fixed to 0x30.
PLL AND OSCILLATOR STATUS REGISTER​

POSR Offset:0x10

BitsFieldTypeResetDescription
31PLL8_LOCKRO0x0PLL8 Lock Status
1 = PLL8 is locked
30PLL7_LOCKRO0x0PLL7 Lock Status
1 = PLL7 is locked
29PLL6_LOCKRO0x0PLL6 Lock Status
1 = PLL6 is locked
28PLL5_LOCKRO0x0PLL5 Lock Status
1 = PLL5 is locked
27PLL4_LOCKRO0x1PLL4 Lock Status
1 = PLL4 is locked
26PLL3_LOCKRO0x0PLL3 Lock Status
1 = PLL3 is locked
25PLL2_LOCKRO0x0PLL2 Lock Status
1 = PLL2 is locked
24PLL1_LOCKRO0x1PLL1 Lock Status
1 = PLL1 is locked
23:18PLL2REFDRW0x0PLL2 Reference Divider (REFDIV)
Decoding: TBD
17:9PLL2FBDRW0x0PLL2 Feedback Divider (FBDIV)
Decoding: TBD
8:0PLL1FBDRW0x30PLL1 Feedback Divider (FBDIV)
Decoding: TBD
SLOW UART (UART 1) CLOCK GENERATION CONTROL REGISTER​

SUCCR Offset:0x14

BitsFieldTypeResetDescription
31:29RSVDRO0Reserved for future use
28:16UARTDIVNRW0x1FBDUART clock generation programmable divider numerator value.
The UART clock is generated using a fractional divider. This divider configuration is common to all UART modules.
15:13RSVDRO0Reserved for future use
12:0UARTDIVDRW0x600UART clock generation programmable divider denominator value.
The UART clock is generated using a fractional divider. This divider configuration is common to all UART modules.
GENERAL PURPOSE CLOCK GENERATION CONTROL REGISTER​

GPCR Offset:0x30

BitsFieldTypeResetDescription
31:16GPCDIVNRW0x0General purpose clock generation programmable divider numerator value.
This clock is generated using a fractional divider, off the VCTCXO clock.
15:0GPCDIVDRW0x0General purpose clock generation programmable divider denominator value.
This clock is generated using a fractional divider, off the VCTCXO clock.
GENERAL PURPOSE CLOCK2 GENERATION CONTROL REGISTER​

GPCR2 Offset:0x48

BitsFieldTypeResetDescription
31:16GPCDIVNRW0x0General purpose clock2 generation programmable divider numerator value.
This clock is generated using a fractional divider, off the VCTCXO clock.
15:0GPCDIVDRW0x0General purpose clock2 generation programmable divider denominator value.
This clock is generated using a fractional divider, off the VCTCXO clock.
SLOW CLOCK CONTROL REGISTER​

SCCR Offset:0x38

BitsFieldTypeResetDescription
31:3RSVDRO0Reserved for future use
2BB_F_SLP_ENRW0x0Force modem into SLEEP mode.
1AFE_CLK_ENRW0x0AFE calibration clock (24 MHz VCXO) enable:
0 = Disable
1 = Enable
0SCSRW0x0Slow Clock Select:
0 = 32kHz internal clock is derived from VCTCXO divider;
1 = 32kHz internal clock uses 32kHz clock input
I2S1 CLOCK GENERATION CONTROL REGISTER​

ISCCR0 Offset:0x40

BitsFieldTypeResetDescription
31SYSCLK_ENRW0x0Enables the I2S clock input to SYSCLK1 generator as well as the output of the generator.
0 = Disable
1 = Enable
30SYSCLK_BASERW0x1Selects the I2S M/N divider input clock frequency
0 = SYSCLKn Generator Base Clock rate is 25.6 MHz
1 = SYSCLKn Generator Base Clock rate is 153.6 MHz.
29BITCLK_ENRW0x0Enables the I2S clock input to the bit clock generator.
0 = Disable
1 = Enable
28:27BITCLK_DIV_2468RW0x3Determine BITCLK1:SYSCLK1 relation:
0x0 = BITCLK1 rate is the SYSCLK1 rate divide by 2;
0x1 = BITCLK1 rate is the SYSCLK1 rate divide by 4;
0x2 = BITCLK1 rate is the SYSCLK1 rate divide by 6;
0x3 = BITCLK1 rate is the SYSCLK1 rate divide by 8
26:15DENOMRW0x40I2S clock generation programmable divider denominator value.
The I2S sysclk is generated using a fractional divider.
14:0NOMRW0x130BI2S clock generation programmable divider numerator value.
The I2S sysclk is generated using a fractional divider.
I2S CLOCK GENERATION CONTROL REGISTER​

ISCCR1 Offset:0x44

BitsFieldTypeResetDescription
31SYSCLK_ENRW0x0Enables the I2S clock input to SYSCLKn generator as well as the output of the generator.
0 = Disable
1 = Enable
30SYSCLK_BASERW0x1Selects the I2S M/N divider input clock frequency:
0 = SYSCLKn Generator Base Clock rate is 25.6 MHz
1 = SYSCLKn Generator Base Clock rate is 153.6 MHz.
29BITCLK_ENRW0x0Enables the I2S clock input to the bit clock generator.
0 = Disable
1 = Enable
28:27BITCLK_DIV_2468RW0x3Determine BITCLKn:SYSCLKn relation:
0x0 = BITCLKn rate is the SYSCLKn rate divide by 2
0x1 = BITCLKn rate is the SYSCLKn rate divide by 4
0x2 = BITCLKn rate is the SYSCLKn rate divide by 6
0x3 = BITCLKn rate is the SYSCLKn rate divide by 8
26:15DENOMRW0x40I2S clock generation programmable divider denominator value.
The I2S sysclk is generated using a fractional divider.
14:0NOMRW0x130BI2S clock generation programmable divider numerator value.
The I2S sysclk is generated using a fractional divider.
RIPC CONTROL REGISTER​

RIPCCR Offset:0x210

BitsFieldTypeResetDescription
31:3RSVDRO0Reserved for future use
2RSTRW0x0R-IPC H/W reset generation:
0 = Release Reset
1 = Reset
1RSVDRO0Reserved for future use
0APBCLKRW0x0R-IPC APB Bus Clock Enable/Disable:
0 = Disable
1 = Enable
ASR SEAGULL/MOHAWK CLOCK GATING REGISTER​

ACGR This register is used by the Application Processor. Offset:0x1024

BitsFieldTypeResetDescription
31:22RSVDRO0Reserved for future use
21CLK_491P5MRW0x1Enable the functional 491.52 MHz clock output.
0 = Disable
1 = Enable
20RSVDRO0Reserved for future use
19WDT_12P8MRW0x0Enable the functional 12.8 MHz clock output of the main to the WatchDogTimer.
0 = Disable
1 = Enable
18CLK_245P7MRW0x1Enable the functional 245 MHz clock output.
0 = Disable
1 = Enable
17RSVDRO0Reserved for future use
16CLK_1228P8MRW0x0Enable the functional 1228 MHz clock output.
0 = Disable
1 = Enable
15CLK_614P4MRW0x1Enable the functional 614.4 MHz clock output.
0 = Disable
1 = Enable
14CLK_819P2MRW0x1Enable the functional 819.2 MHz clock output.
0 = Disable
1 = Enable
13CLK_307P2MRW0x1Enable the functional 307.2 MHz clock output.
0 = Disable
1 = Enable
12CLK_102P4MRW0x0Enable the functional 102.4 MHz clock output.
0 = Disable
1 = Enable
11CLK_51P2_APRW0x0Enable the functional 51.2 MHz clock output for AP PMU and AP Peripherals.
0 = Disable
1 = Enable
10CLK_47P2MRW0x0Enable the functional 47.2 MHz clock output.
0 = Disable
1 = Enable
9GPCRW0x0Enable the M/N clock generator of the VCXO clock configured through GPCR, the clock is output to VCXO_OUT PAD func3
0 = Disable
1 = Enable
8AP_FUARTRW0x0Enable the functional fast UART clock output (58.5 MHz) of the main to the Application Processor APB portion.
0 = Disable
1 = Enable
7CLK_51P2MRW0x0Enable the functional 51.2 MHz clock output for APB peripherals
0 = Disable
1 = Enable
6AP_TWSIRW0x0Enable the 32M clock of the functional TWSI clock output of the main to the Application Processor APB portion.
0 = Disable
1 = Enable
5CLK_204P8MRW0x0Enable the functional 204.8 MHz clock output.
0 = Disable
1 = Enable
4CLK_25P6MRW0x1Enable the functional 25.6 MHz clock output.
0 = Disable
1 = Enable
3CLK_12P8MRW0x0Enable the functional 12.8 MHz clock output.
0 = Disable
1 = Enable
2CLK_6P4MRW0x0Enable the functional 6.4 MHz clock output
0 = Disable
1 = Enable
1AP_SUARTRW0x0Enable the functional M/N slow UART clock output (configured through SUCCR0/1) of the main to the Application Processor APB portion. This is the UART slow clock (14.74 MHz) source enable.
0 = Disable
1 = Enable
0CLK_409P6MRW0x1Enable the functional 409.6 MHz clock output.
0 = Disable
1 = Enable
APB CLOCK SOURCE CONTROL REGISTER​

APBCSCR This register is used by the Application Processor. Offset:0x1050

BitsFieldTypeResetDescription
31:2RSVDRO0Reserved for future use
1:0APB_CLKRW0x0System APB Clk Source Selection
0x0 or 0x2 = 25.6 MHz;
0x1 = 51.2 MHz;
0x3 = 102.4 MHz
PM_MN_CLK CONTROL REGISTER​

PM_MN_CLK Offset:0x10A4

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:5PM_MN_CLK2_SELRW0x0PM_MN_CLK2_SEL
0x0 = vctcxo;
0x1 = pll2_div5 (600MHz);
0x2 = clk_24m_rtc in SCS Mode
4PM_MN_CLK2_SW_ENRW0x0PM_MN_CLK2_SW_EN:
0 = Disable
1 = Enable
3RSVDRO0Reserved for future use
2:1PM_MN_CLK_SELRW0x0PM_MN_CLK_SEL:
0x0 = vctcxo;
0x1 = 614M;
0x2 = clk_24m_rtc in SCS Mode
0PM_MN_CLK_SW_ENRW0x0PM_MN_CLK_SW_EN:
0 = Disable
1 = Enable
SLOW UART (UART 1) CLOCK GENERATION CONTROL REGISTER​

SUCCR_1 Offset:0x10B0

BitsFieldTypeResetDescription
31:29RSVDRO0Reserved for future use
28:16UARTDIVN_1RW0x1800UART clock generation programmable divider numerator value.
The UART clock is generated using a fractional divider. This divider configuration is common to all UART modules.
15:13RSVDRO0Reserved for future use
12:0UARTDIVD_1RW0x3C0UART clock generation programmable divider denominator value.
The UART clock is generated using a fractional divider. This divider configuration is common to all UART modules.
I2S0_SYSCLK CLOCK CONTROL REGISTER​

I2S0_SYSCLK_CTRL I2S SYSCLK0 denominator and numerator registers. Offset:0x1100

BitsFieldTypeResetDescription
31:16I2S_SYSCLK0_DENOMRW0x208I2S SYSCLK0 divider denominator
15:0I2S_SYSCLK0_NOMRW0x1800I2S SYSCLK0 divider numerator
I2S2_SYSCLK CLOCK CONTROL REGISTER​

I2S2_SYSCLK_CTRL I2S SYSCLK2 denominator and numerator registers. Offset:0x1104

BitsFieldTypeResetDescription
31:16I2S_SYSCLK2_DENOMRW0x208I2S SYSCLK2 divider denominator
15:0I2S_SYSCLK2_NOMRW0x1800I2S SYSCLK2 divider numerator
I2S3_SYSCLK CLOCK CONTROL REGISTER​

I2S3_SYSCLK_CTRL I2S SYSCLK3 denominator and numerator registers. Offset:0x1108

BitsFieldTypeResetDescription
31:16I2S_SYSCLK3_DENOMRW0x208I2S SYSCLK3 divider denominator
15:0I2S_SYSCLK3_NOMRW0x1800I2S SYSCLK3 divider numerator
I2S4_SYSCLK CLOCK CONTROL REGISTER​

I2S4_SYSCLK_CTRL I2S SYSCLK4 denominator and numerator registers. Offset:0x110C

BitsFieldTypeResetDescription
31:16I2S_SYSCLK4_DENOMRW0x208I2S SYSCLK4 divider denominator
15:0I2S_SYSCLK4_NOMRW0x1800I2S SYSCLK4 divider numerator
I2S5_SYSCLK CLOCK CONTROL REGISTER​

I2S5_SYSCLK_CTRL I2S SYSCLK5 denominator and numerator registers. Offset:0x1110

BitsFieldTypeResetDescription
31:16I2S_SYSCLK5_DENOMRW0x208I2S SYSCLK5 divider denominator
15:0I2S_SYSCLK5_NOMRW0x1800I2S SYSCLK5 divider numerator
I2Sn_SYSCLK CONTROL REGISTER​

I2S_SYSCTRL I2S_SYSCTRL register for I2S SYSCLK0 to I2S SYSCLK5. Offset:0x1114

BitsFieldTypeResetDescription
31:24RSVDRO0Reserved for future use
23I2S_SYSCLK5_SELRW0x0I2S SYSCLK5 output clock select:
0x0 = output from divider div_clk
0x1 = output from vctcxo clock
22I2S_SYSCLK5_ENRW0x0I2S SYSCLK5 enable:
0 = Disable
1 = Enable
21I2S_SYSCLK5_DIV_SEL_1RW0x0I2S SYSCLK5 divider source clock select_1:
0x0 = i2s_sysclk5_div_sel_0 clock
0x1 = vctcxo clock
20I2S_SYSCLK5_DIV_SEL_0RW0x0I2S SYSCLK5 divider source clock select_0:
0x0 = 614MHz
0x1 = pll2_div5
19I2S_SYSCLK4_SELRW0x0I2S SYSCLK4 output clock select:
0x0 = output from divider div_clk
0x1 = output from vctcxo clock
18I2S_SYSCLK4_ENRW0x0I2S SYSCLK4 enable:
0 = Disable
1 = Enable
17I2S_SYSCLK4_DIV_SEL_1RW0x0I2S SYSCLK4 divider source clock select_1:
0x0 = i2s_sysclk4_div_sel_0 clock
0x1 = vctcxo clock
16I2S_SYSCLK4_DIV_SEL_0RW0x0I2S SYSCLK4 divider source clock select_0:
0x0 = 614MHz
0x1 = pll2_div5
15I2S_SYSCLK3_SELRW0x0I2S SYSCLK3 output clock select:
0x0 = output from divider div_clk
0x1 = output from vctcxo clock
14I2S_SYSCLK3_ENRW0x0I2S SYSCLK3 enable:
0 = Disable
1 = Enable
13I2S_SYSCLK3_DIV_SEL_1RW0x0I2S SYSCLK3 divider source clock select_1:
0x0 = i2s_sysclk3_div_sel_0 clock
0x1 = vctcxo clock
12I2S_SYSCLK3_DIV_SEL_0RW0x0I2S SYSCLK3 divider source clock select_0:
0x0 = 614MHz
0x1 = pll2_div5
11:9RSVDRO0Reserved for future use
8I2S_SYSCLK2_SEL_1RW0x0I2S SYSCLK2 final output clock select:
0x0 = output from i2s_sc_apb, refer to isccr1
0x1 = output from i2s_sysclk2_sel_0 clock
7I2S_SYSCLK2_SEL_0RW0x0I2S SYSCLK2 output clock select_0:
0x0 = output from divider div_clk
0x1 = output from vctcxo clock
6I2S_SYSCLK2_ENRW0x0I2S SYSCLK2 enable:
0 = Disable
1 = Enable
5I2S_SYSCLK2_DIV_SEL_1RW0x0I2S SYSCLK2 divider source clock select_1:
0x0 = i2s_sysclk2_div_sel_0 clock
0x1 = vctcxo clock
4I2S_SYSCLK2_DIV_SEL_0RW0x0I2S SYSCLK2 divider source clock select_0:
0x0 = 614MHz
0x1 = pll2_div5
3I2S_SYSCLK0_SELRW0x0I2S SYSCLK0 output clock select:
0x0 = output from divider div_clk
0x1 = output from vctcxo clock
2I2S_SYSCLK0_ENRW0x0I2S SYSCLK0 enable:
0 = Disable
1 = Enable
1I2S_SYSCLK0_DIV_SEL_1RW0x0I2S SYSCLK0 divider source clock select_1:
0x0 = i2s_sysclk0_div_sel_0 clock
0x1 = vctcxo clock
0I2S_SYSCLK0_DIV_SEL_0RW0x0I2S SYSCLK0 divider source clock select_0:
0x0 = 614MHz
0x1 = pll2_div5

APB_SPARE​

PLL1 SW CONTROL REGISTER​

APB_SPARE1_REG Offset:0x100

BitsFieldTypeResetDescription
31:24PLL1_REG4RW0x0BPLL1 Register 4 Configuration
23:16PLL1_REG3RW0x33PLL1 Register 3 Configuration
15:8PLL1_REG2RW0x0CPLL1 Register 2 Configuration
7:0PLL1_REG1RW0xCCPLL1 Register 1 Configuration
PLL1 SW CONTROL REGISTER​

APB_SPARE2_REG Offset:0x104

BitsFieldTypeResetDescription
31PLL1_DIV64_ENRW0x1PLL1_DIV64_EN:
0 = Disable
1 = Enable
30PLL1_CKTEST_ENRW0x0PLL1_CKTEST_EN:
0 = Disable
1 = Enable
29PLL1_DTEST_ENRW0x0PLL1_DTEST_EN:
0 = Disable
1 = Enable
28PLL1_ATEST_ENRW0x0PLL1_ATEST_EN:
0 = Disable
1 = Enable
27:23PLL1_POST_MMDRW0x0PLL1_POST_MMD:
MMD CLK = PLL1 / (this field + 1)
22PLL1_POST_MMD_ENRW0x0PLL1_POST_MMD_EN:
0 = Disable
1 = Enable
21PLL1_DIV10_ENRW0x1PLL1_DIV10_EN:
0 = Disable
1 = Enable
20:17PLL1_MON_CFGRW0x0PLL1_MON_CFG:
[17] = 1: monitor enable
[20:18]: monitor divider
16PLL1_PURW0x0PLL1_PU:
0 = Disable
1 = Enable
15:8PLL1_REG0RW0xCDPLL1 Register 0 Configuration
7PLL1_DIV8_ENRW0x1PLL1_DIV8_EN:
0 = Disable
1 = Enable
6PLL1_DIV7_ENRW0x1PLL1_DIV7_EN:
0 = Disable
1 = Enable
5PLL1_DIV6_ENRW0x1PLL1_DIV6_EN:
0 = Disable
1 = Enable
4PLL1_DIV5_ENRW0x1PLL1_DIV5_EN:
0 = Disable
1 = Enable
3PLL1_DIV4_ENRW0x1PLL1_DIV4_EN:
0 = Disable
1 = Enable
2PLL1_DIV3_ENRW0x1PLL1_DIV3_EN:
0 = Disable
1 = Enable
1PLL1_DIV2_ENRW0x1PLL1_DIV2_EN:
0 = Disable
1 = Enable
0PLL1_DIV1_ENRW0x0PLL1_DIV1_EN:
0 = Disable
1 = Enable
PLL1 SW CONTROL REGISTER​

APB_SPARE3_REG Offset:0x108

BitsFieldTypeResetDescription
31:24PLL1_REG8RW0xA0PLL1 Register 8 Configuration
23:16PLL1_REG7RW0x55PLL1 Register 7 Configuration
15:8PLL1_REG6RW0x89PLL1 Register 6 Configuration
7:0PLL1_REG5RW0x89PLL1 Register 5 Configuration
PLL2 SW CONTROL REGISTER​

APB_SPARE7_REG Offset:0x118

BitsFieldTypeResetDescription
31:24PLL2_REG4RW0x0BPLL2 Register 4 Configuration
23:16PLL2_REG3RW0x3EPLL2 Register 3 Configuration
15:8PLL2_REG2RW0x20PLL2 Register 2 Configuration
7:0PLL2_REG1RW0x00PLL2 Register 1 Configuration
PLL2 SW CONTROL REGISTER​

APB_SPARE8_REG Offset:0x11C

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30PLL2_CKTEST_ENRW0x0PLL2_CKTEST_EN:
0 = Disable
1 = Enable
29PLL2_DTEST_ENRW0x0PLL2_DTEST_EN:
0 = Disable
1 = Enable
28PLL2_ATEST_ENRW0x0PLL2_ATEST_EN:
0 = Disable
1 = Enable
27:23PLL2_POST_MMDRW0x0PLL2_POST_MMD:
MMD CLK = PLL2 / (this field + 1)
22PLL2_POST_MMD_ENRW0x0PLL2_POST_MMD_EN:
0 = Disable
1 = Enable
21PLL2_DIV10_ENRW0x0PLL2_DIV10_EN:
0 = Disable
1 = Enable
20:17PLL2_MON_CFGRW0x0PLL2_MON_CFG:
[17] = 1: monitor enable
[20:18]: monitor divider
16PLL2_PURW0x0PLL2_PU:
0 = Disable
1 = Enable
15:8PLL2_REG0RW0x00PLL2 Register 0 Configuration
7PLL2_DIV8_ENRW0x0PLL2_DIV8_EN:
0 = Disable
1 = Enable
6PLL2_DIV7_ENRW0x0PLL2_DIV7_EN:
0 = Disable
1 = Enable
5PLL2_DIV6_ENRW0x0PLL2_DIV6_EN:
0 = Disable
1 = Enable
4PLL2_DIV5_ENRW0x0PLL2_DIV5_EN:
0 = Disable
1 = Enable
3PLL2_DIV4_ENRW0x0PLL2_DIV4_EN:
0 = Disable
1 = Enable
2PLL2_DIV3_ENRW0x0PLL2_DIV3_EN:
0 = Disable
1 = Enable
1PLL2_DIV2_ENRW0x0PLL2_DIV2_EN:
0 = Disable
1 = Enable
0PLL2_DIV1_ENRW0x0PLL2_DIV1_EN:
0 = Disable
1 = Enable
PLL2 SW CONTROL REGISTER​

APB_SPARE9_REG Offset:0x120

BitsFieldTypeResetDescription
31:24PLL2_REG8RW0xA0PLL2 Register 8 Configuration
23:16PLL2_REG7RW0x55PLL2 Register 7 Configuration
15:8PLL2_REG6RW0x8CPLL2 Register 6 Configuration
7:0PLL2_REG5RW0x8CPLL2 Register 5 Configuration
PLL3 SW CONTROL REGISTER​

APB_SPARE10_REG Offset:0x124

BitsFieldTypeResetDescription
31:24PLL3_REG4RW0x0BPLL3 Register 4 Configuration
23:16PLL3_REG3RW0x2DPLL3 Register 3 Configuration
15:8PLL3_REG2RW0x35PLL3 Register 2 Configuration
7:0PLL3_REG1RW0x55PLL3 Register 1 Configuration
PLL3 SW CONTROL REGISTER​

APB_SPARE11_REG Offset:0x128

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30PLL3_CKTEST_ENRW0x0PLL3_CKTEST_EN:
0 = Disable
1 = Enable
29PLL3_DTEST_ENRW0x0PLL3_DTEST_EN:
0 = Disable
1 = Enable
28PLL3_ATEST_ENRW0x0PLL3_ATEST_EN:
0 = Disable
1 = Enable
27:23PLL3_POST_MMDRW0x0PLL3_POST_MMD:
MMD CLK = PLL3 / (this field + 1)
22PLL3_POST_MMD_ENRW0x0PLL3_POST_MMD_EN:
0 = Disable
1 = Enable
21PLL3_DIV10_ENRW0x0PLL3_DIV10_EN:
0 = Disable
1 = Enable
20:17PLL3_MON_CFGRW0x0PLL3_MON_CFG:
[17] = 1: monitor enable
[20:18]: monitor divider
16PLL3_PURW0x0PLL3_PU:
0 = Disable
1 = Enable
15:8PLL3_REG0RW0x55PLL3 Register 0 Configuration
7PLL3_DIV8_ENRW0x0PLL3_DIV8_EN:
0 = Disable
1 = Enable
6PLL3_DIV7_ENRW0x0PLL3_DIV7_EN:
0 = Disable
1 = Enable
5PLL3_DIV6_ENRW0x0PLL3_DIV6_EN:
0 = Disable
1 = Enable
4PLL3_DIV5_ENRW0x0PLL3_DIV5_EN:
0 = Disable
1 = Enable
3PLL3_DIV4_ENRW0x0PLL3_DIV4_EN:
0 = Disable
1 = Enable
2PLL3_DIV3_ENRW0x0PLL3_DIV3_EN:
0 = Disable
1 = Enable
1PLL3_DIV2_ENRW0x0PLL3_DIV2_EN:
0 = Disable
1 = Enable
0PLL3_DIV1_ENRW0x0PLL3_DIV1_EN:
0 = Disable
1 = Enable
PLL3 SW CONTROL REGISTER​

APB_SPARE12_REG Offset:0x12C

BitsFieldTypeResetDescription
31:24PLL3_REG8RW0xA0PLL3 Register 8 Configuration
23:16PLL3_REG7RW0x55PLL3 Register 7 Configuration
15:8PLL3_REG6RW0x87PLL3 Register 6 Configuration
7:0PLL3_REG5RW0x87PLL3 Register 5 Configuration
PLL4 SW CONTROL REGISTER​

APB_SPARE13_REG Offset:0x130

BitsFieldTypeResetDescription
31:24PLL4_REG4RW0x0BPLL4 Register 4 Configuration
23:16PLL4_REG3RW0x2DPLL4 Register 3 Configuration
15:8PLL4_REG2RW0x35PLL4 Register 2 Configuration
7:0PLL4_REG1RW0x55PLL4 Register 1 Configuration
PLL4 SW CONTROL REGISTER​

APB_SPARE14_REG Offset:0x134

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30PLL4_CKTEST_ENRW0x0PLL4_CKTEST_EN:
0 = Disable
1 = Enable
29PLL4_DTEST_ENRW0x0PLL4_DTEST_EN:
0 = Disable
1 = Enable
28PLL4_ATEST_ENRW0x0PLL4_ATEST_EN:
0 = Disable
1 = Enable
27:23PLL4_POST_MMDRW0x0PLL4_POST_MMD:
MMD CLK = PLL4 / (this field + 1)
22PLL4_POST_MMD_ENRW0x0PLL4_POST_MMD_EN:
0 = Disable
1 = Enable
21PLL4_DIV10_ENRW0x0PLL4_DIV10_EN:
0 = Disable
1 = Enable
20:17PLL4_MON_CFGRW0x0PLL4_MON_CFG:
[17] = 1: monitor enable
[20:18]: monitor divider
16PLL4_PURW0x0PLL4_PU:
0 = Disable
1 = Enable
15:8PLL4_REG0RW0x55PLL4 Register 0 Configuration
7PLL4_DIV8_ENRW0x0PLL4_DIV8_EN:
0 = Disable
1 = Enable
6PLL4_DIV7_ENRW0x0PLL4_DIV7_EN:
0 = Disable
1 = Enable
5PLL4_DIV6_ENRW0x0PLL4_DIV6_EN:
0 = Disable
1 = Enable
4PLL4_DIV5_ENRW0x0PLL4_DIV5_EN:
0 = Disable
1 = Enable
3PLL4_DIV4_ENRW0x0PLL4_DIV4_EN:
0 = Disable
1 = Enable
2PLL4_DIV3_ENRW0x0PLL4_DIV3_EN:
0 = Disable
1 = Enable
1PLL4_DIV2_ENRW0x0PLL4_DIV2_EN:
0 = Disable
1 = Enable
0PLL4_DIV1_ENRW0x0PLL4_DIV1_EN:
0 = Disable
1 = Enable
PLL4 SW CONTROL REGISTER​

APB_SPARE15_REG Offset:0x138

BitsFieldTypeResetDescription
31:24PLL4_REG8RW0xA0PLL4 Register 8 Configuration
23:16PLL4_REG7RW0x55PLL4 Register 7 Configuration
15:8PLL4_REG6RW0x87PLL4 Register 6 Configuration
7:0PLL4_REG5RW0x87PLL4 Register 5 Configuration
PLL5 SW CONTROL REGISTER​

APB_SPARE16_REG Offset:0x13C

BitsFieldTypeResetDescription
31:24PLL5_REG4RW0x0BPLL5 Register 4 Configuration
23:16PLL5_REG3RW0x29PLL5 Register 3 Configuration
15:8PLL5_REG2RW0x2APLL5 Register 2 Configuration
7:0PLL5_REG1RW0xAAPLL5 Register 1 Configuration
PLL5 SW CONTROL REGISTER​

APB_SPARE17_REG Offset:0x140

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30PLL5_CKTEST_ENRW0x0PLL5_CKTEST_EN:
0 = Disable
1 = Enable
29PLL5_DTEST_ENRW0x0PLL5_DTEST_EN:
0 = Disable
1 = Enable
28PLL5_ATEST_ENRW0x0PLL5_ATEST_EN:
0 = Disable
1 = Enable
27:23PLL5_POST_MMDRW0x0PLL5_POST_MMD:
MMD CLK = PLL5 / (this field + 1)
22PLL5_POST_MMD_ENRW0x0PLL5_POST_MMD_EN:
0 = Disable
1 = Enable
21PLL5_DIV10_ENRW0x0PLL5_DIV10_EN:
0 = Disable
1 = Enable
20:17PLL5_MON_CFGRW0x0PLL5_MON_CFG:
[17] = 1: monitor enable
[20:18]: monitor divider
16PLL5_PURW0x0PLL5_PU:
0 = Disable
1 = Enable
15:8PLL5_REG0RW0xABPLL5 Register 0 Configuration
7PLL5_DIV8_ENRW0x0PLL5_DIV8_EN:
0 = Disable
1 = Enable
6PLL5_DIV7_ENRW0x0PLL5_DIV7_EN:
0 = Disable
1 = Enable
5PLL5_DIV6_ENRW0x0PLL5_DIV6_EN:
0 = Disable
1 = Enable
4PLL5_DIV5_ENRW0x0PLL5_DIV5_EN:
0 = Disable
1 = Enable
3PLL5_DIV4_ENRW0x0PLL5_DIV4_EN:
0 = Disable
1 = Enable
2PLL5_DIV3_ENRW0x0PLL5_DIV3_EN:
0 = Disable
1 = Enable
1PLL5_DIV2_ENRW0x0PLL5_DIV2_EN:
0 = Disable
1 = Enable
0PLL5_DIV1_ENRW0x0PLL5_DIV1_EN:
0 = Disable
1 = Enable
PLL5 SW CONTROL REGISTER​

APB_SPARE18_REG Offset:0x144

BitsFieldTypeResetDescription
31:24PLL5_REG8RW0xA0PLL5 Register 8 Configuration
23:16PLL5_REG7RW0x55PLL5 Register 7 Configuration
15:8PLL5_REG6RW0x86PLL5 Register 6 Configuration
7:0PLL5_REG5RW0x86PLL5 Register 5 Configuration
PLL6 SW CONTROL REGISTER​

APB_SPARE19_REG Offset:0x148

BitsFieldTypeResetDescription
31:24PLL6_REG4RW0x0BPLL6 Register 4 Configuration
23:16PLL6_REG3RW0x42PLL6 Register 3 Configuration
15:8PLL6_REG2RW0x2APLL6 Register 2 Configuration
7:0PLL6_REG1RW0xAAPLL6 Register 1 Configuration
PLL6 SW CONTROL REGISTER​

APB_SPARE20_REG Offset:0x14C

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30PLL6_CKTEST_ENRW0x0PLL6_CKTEST_EN:
0 = Disable
1 = Enable
29PLL6_DTEST_ENRW0x0PLL6_DTEST_EN:
0 = Disable
1 = Enable
28PLL6_ATEST_ENRW0x0PLL6_ATEST_EN:
0 = Disable
1 = Enable
27:23PLL6_POST_MMDRW0x1EPLL6_POST_MMD:
MMD CLK = PLL6 / (this field + 1)
22PLL6_POST_MMD_ENRW0x0PLL6_POST_MMD_EN:
0 = Disable
1 = Enable
21PLL6_DIV10_ENRW0x0PLL6_DIV10_EN:
0 = Disable
1 = Enable
20:17PLL6_MON_CFGRW0x0PLL6_MON_CFG:
[17] = 1: monitor enable
[20:18]: monitor divider
16PLL6_PURW0x0PLL6_PU:
0 = Disable
1 = Enable
15:8PLL6_REG0RW0xABPLL6 Register 0 Configuration
7PLL6_DIV8_ENRW0x0PLL6_DIV8_EN:
0 = Disable
1 = Enable
6PLL6_DIV7_ENRW0x0PLL6_DIV7_EN:
0 = Disable
1 = Enable
5PLL6_DIV6_ENRW0x0PLL6_DIV6_EN:
0 = Disable
1 = Enable
4PLL6_DIV5_ENRW0x0PLL6_DIV5_EN:
0 = Disable
1 = Enable
3PLL6_DIV4_ENRW0x0PLL6_DIV4_EN:
0 = Disable
1 = Enable
2PLL6_DIV3_ENRW0x0PLL6_DIV3_EN:
0 = Disable
1 = Enable
1PLL6_DIV2_ENRW0x0PLL6_DIV2_EN:
0 = Disable
1 = Enable
0PLL6_DIV1_ENRW0x0PLL6_DIV1_EN:
0 = Disable
1 = Enable
PLL6 SW CONTROL REGISTER​

APB_SPARE21_REG Offset:0x150

BitsFieldTypeResetDescription
31:24PLL6_REG8RW0xA0PLL6 Register 8 Configuration
23:16PLL6_REG7RW0x55PLL6 Register 7 Configuration
15:8PLL6_REG6RW0x8EPLL6 Register 6 Configuration
7:0PLL6_REG5RW0x8EPLL6 Register 5 Configuration
BG_RO​

APB_SPARE22_REG Offset:0x154

BitsFieldTypeResetDescription
31:29PLL8_RDORO0x0Read-only status for PLL8 (RDO)
28:26PLL7_RDORO0x0Read-only status for PLL7 (RDO)
25:23PLL6_RDORO0x0Read-only status for PLL6 (RDO)
22:20PLL5_RDORO0x0Read-only status for PLL5 (RDO)
19:17PLL4_RDORO0x0Read-only status for PLL4 (RDO)
16:14PLL3_RDORO0x0Read-only status for PLL3 (RDO)
13:11PLL2_RDORO0x0Read-only status for PLL2 (RDO)
10:8PLL1_RDORO0x0Read-only status for PLL1 (RDO)
7:0RSVDRO0Reserved for future use
PLL7 SW CONTROL REGISTER​

APB_SPARE23_REG Offset:0x158

BitsFieldTypeResetDescription
31:24PLL7_REG4RW0x0BPLL7 Register 4 Configuration
23:16PLL7_REG3RW0x3APLL7 Register 3 Configuration
15:8PLL7_REG2RW0x15PLL7 Register 2 Configuration
7:0PLL7_REG1RW0x55PLL7 Register 1 Configuration
PLL7 SW CONTROL REGISTER​

APB_SPARE24_REG Offset:0x15C

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30PLL7_CKTEST_ENRW0x0PLL7_CKTEST_EN:
0 = Disable
1 = Enable
29PLL7_DTEST_ENRW0x0PLL7_DTEST_EN:
0 = Disable
1 = Enable
28PLL7_ATEST_ENRW0x0PLL7_ATEST_EN:
0 = Disable
1 = Enable
27:23PLL7_POST_MMDRW0x0PLL7_POST_MMD:
MMD CLK = PLL7 / (this field + 1)
22PLL7_POST_MMD_ENRW0x0PLL7_POST_MMD_EN:
0 = Disable
1 = Enable
21PLL7_DIV10_ENRW0x0PLL7_DIV10_EN:
0 = Disable
1 = Enable
20:17PLL7_MON_CFGRW0x0PLL7_MON_CFG:
[17] = 1: monitor enable
[20:18]: monitor divider
16PLL7_PURW0x0PLL7_PU:
0 = Disable
1 = Enable
15:8PLL7_REG0RW0x55PLL7 Register 0 Configuration
7PLL7_DIV8_ENRW0x0PLL7_DIV8_EN:
0 = Disable
1 = Enable
6PLL7_DIV7_ENRW0x0PLL7_DIV7_EN:
0 = Disable
1 = Enable
5PLL7_DIV6_ENRW0x0PLL7_DIV6_EN:
0 = Disable
1 = Enable
4PLL7_DIV5_ENRW0x0PLL7_DIV5_EN:
0 = Disable
1 = Enable
3PLL7_DIV4_ENRW0x0PLL7_DIV4_EN:
0 = Disable
1 = Enable
2PLL7_DIV3_ENRW0x0PLL7_DIV3_EN:
0 = Disable
1 = Enable
1PLL7_DIV2_ENRW0x0PLL7_DIV2_EN:
0 = Disable
1 = Enable
0PLL7_DIV1_ENRW0x0PLL7_DIV1_EN:
0 = Disable
1 = Enable
PLL7 SW CONTROL REGISTER​

APB_SPARE25_REG Offset:0x160

BitsFieldTypeResetDescription
31:24PLL7_REG8RW0xA0PLL7 Register 8 Configuration
23:16PLL7_REG7RW0x55PLL7 Register 7 Configuration
15:8PLL7_REG6RW0x8BPLL7 Register 6 Configuration
7:0PLL7_REG5RW0x8BPLL7 Register 5 Configuration
PLL8 SW CONTROL REGISTER​

APB_SPARE33_REG Offset:0x180

BitsFieldTypeResetDescription
31:24PLL8_REG4RW0x0BPLL8 Register 4 Configuration
23:16PLL8_REG3RW0x29PLL8 Register 3 Configuration
15:8PLL8_REG2RW0x2APLL8 Register 2 Configuration
7:0PLL8_REG1RW0xAAPLL8 Register 1 Configuration
PLL8 SW CONTROL REGISTER​

APB_SPARE34_REG Offset:0x184

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30PLL8_CKTEST_ENRW0x0PLL8_CKTEST_EN:
0 = Disable
1 = Enable
29PLL8_DTEST_ENRW0x0PLL8_DTEST_EN:
0 = Disable
1 = Enable
28PLL8_ATEST_ENRW0x0PLL8_ATEST_EN:
0 = Disable
1 = Enable
27:23PLL8_POST_MMDRW0x0PLL8_POST_MMD:
MMD CLK = PLL8 / (this field + 1)
22PLL8_POST_MMD_ENRW0x0PLL8_POST_MMD_EN:
0 = Disable
1 = Enable
21PLL8_DIV10_ENRW0x0PLL8_DIV10_EN:
0 = Disable
1 = Enable
20:17PLL8_MON_CFGRW0x0PLL8_MON_CFG:
[17] = 1: monitor enable
[20:18]: monitor divider
16PLL8_PURW0x0PLL8_PU:
0 = Disable
1 = Enable
15:8PLL8_REG0RW0xABPLL8 Register 0 Configuration
7PLL8_DIV8_ENRW0x0PLL8_DIV8_EN:
0 = Disable
1 = Enable
6PLL8_DIV7_ENRW0x0PLL8_DIV7_EN:
0 = Disable
1 = Enable
5PLL8_DIV6_ENRW0x0PLL8_DIV6_EN:
0 = Disable
1 = Enable
4PLL8_DIV5_ENRW0x0PLL8_DIV5_EN:
0 = Disable
1 = Enable
3PLL8_DIV4_ENRW0x0PLL8_DIV4_EN:
0 = Disable
1 = Enable
2PLL8_DIV3_ENRW0x0PLL8_DIV3_EN:
0 = Disable
1 = Enable
1PLL8_DIV2_ENRW0x0PLL8_DIV2_EN:
0 = Disable
1 = Enable
0PLL8_DIV1_ENRW0x0PLL8_DIV1_EN:
0 = Disable
1 = Enable
PLL8 SW CONTROL REGISTER​

APB_SPARE35_REG Offset:0x188

BitsFieldTypeResetDescription
31:24PLL8_REG8RW0xA0PLL8 Register 8 Configuration
23:16PLL8_REG7RW0x55PLL8 Register 7 Configuration
15:8PLL8_REG6RW0x86PLL8 Register 6 Configuration
7:0PLL8_REG5RW0x86PLL8 Register 5 Configuration

APBCLOCK​

CLOCK/RESET CONTROL REGISTER FOR UART​

APBC_UARTn_CLK_RST(n = 0, 2~10) Offset:0x00/0x04/0x24/0x70/0x74/0x78/0x94/0x98/0x9C/0x154

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 57.6 MHz
0x1 = 14.74 MHz
0x2 = 48 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1UART Reset Generation
This field resets both APB and Functional domains.
0 = Release Reset
1 = Reset
1FNCLKRW0x0UART Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0UART APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR GPIO​

APBC_GPIO_CLK_RST Offset:0x8

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 24 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1GPIO Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1FNCLKRW0x0GPIO Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0GPIO APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR PWM​

APBC_PWMn_CLK_RST(n = 0~19) The PWM unit functional clock must be gracefully shut down. To do this, disable the functional clock first before disabling the APB clock. Offset:0x0C/0x10/0x14/0x18/0xA8/0xAC/0xB0/0xB4/0xB8/0xBC/0xC0/0xC4/0xC8/0xCC/0xD0/0xD4/0xD8/0xDC/0xE0/0xE4

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 12.8 MHz
0x1 = 32 kHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1PWM Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1FNCLKRW0x0PWM Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0PWM APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR SSP​

APBC_SSPn_CLK_RST(n = 0/1/3) Offset:0x158/0x15C/0x7C

BitsFieldTypeResetDescription
31:8RSVDRO0Reserved for future use
7SEL_SSP_FUNC_CLKRW0x0AC97 Clock Switch:
This bit enables the SSP module to switch clocks internally.
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 6.4 MHz
0x1 = 12.8 MHz
0x2 = 25.6 MHz
0x3 = 51.2 MHz
0x4 = 3.2 MHz
0x5 = 1.6 MHz
0x6 = 800 kHz
0x7 = 1 MHz or i2s_bitclk (MN divided from 307.2 MHz)
3SEL_1MHZRW0x0SSP 1MHz clock or i2s_bitclk selection:
(MN divided from PLL_div8 307.2 MHz)
0x0 = 1 MHz
0x1 = i2s_bitclk
2RSTRW0x1SSP Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1FNCLKRW0x0SSP Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0SSP APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR RTC​

APBC_RTC_CLK_RST Offset:0x28

BitsFieldTypeResetDescription
31:8RSVDRO0Reserved for future use
7PM_POWER_SENSORRW0x0Power Enabled:
This field enables the register read/writes for the RTC module by indicating power enable.
Set this field to 0x1 before enabling RTC operations.
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 32 kHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x0RTC Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1FNCLKRW0x1RTC Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0RTC APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR TWSI​

APBC_TWSIn_CLK_RST(n = 0/1/2/4/5/6/8) Offset:0x2C/0x30/0x38/0x40/0x4C/0x60/0x20

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 31.5 MHz
0x1 = 51.2 MHz
0x2 = 61.44 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1TWSI Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1FNCLKRW0x0TWSI0 Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0TWSI0 APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR TIMER​

APBC_TIMERSn_CLK_RST(n = 0~7) Offset:0x34/0x44/0x11C/0x120/0x124/0x128/0x12C/0x130

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 12.8 MHz
0x1 = 32 kHz
0x2 = 6.4 MHz
0x3 = 3.00 MHz
0x4 = 1 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1Timers Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1FNCLKRW0x0Timers Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0Timers APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR AIB​

APBC_AIB_CLK_RST Offset:0x3C

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 24 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1AIB Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1FNCLKRW0x0AIB Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0AIB APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR ONE-WIRE​

APBC_ONEWIRE_CLK_RST Offset:0x48

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 24 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1One-Wire Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1FNCLKRW0x0One-Wire Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0One-Wire APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR SSPA​

APBC_SSPAn_CLK_RST(n = 0~5) Offset:0x80/0x84/0x88/0x8C/0x160/0x164

BitsFieldTypeResetDescription
31:8RSVDRO0Reserved for future use
7SEL_SSP_FUNC_CLKRW0x0AC97 Clock Switch:
This bit enables the SSP module to switch clocks internally.
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 6.4 MHz
0x1 = 12.8 MHz
0x2 = 25.6 MHz
0x3 = 51.2 MHz
0x4 = 3.2 MHz
0x5 = 1.6 MHz
0x6 = 800 kHz
0x7 = 1 MHz or i2s_bitclk (MN divided from 307.2 MHz)
3SEL_1MHZRW0x0SSPA 1 MHz clock or i2s_bitclk selection:
(Source: MN divided from PLL_div8 307.2 MHz)
0x0 = 1 MHz
0x1 = i2s_bitclk
2RSTRW0x1SSPA Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1FNCLKRW0x0SSPA Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0SSPA APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR DRO​

APBC_DRO_CLK_RST Offset:0x58

BitsFieldTypeResetDescription
31:3RSVDRO0Reserved for future use
2RSTRW0x1DRO Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1RSVDRO0Reserved for future use
0APBCLKRW0x0DRO APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR IR​

APBC_IR_CLK_RST Offset:0x5C

BitsFieldTypeResetDescription
31:3RSVDRO0Reserved for future use
2RSTRW0x1IR Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1RSVDRO0Reserved for future use
0APBCLKRW0x0IR APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK CONTROL REGISTER FOR GENERIC COUNTER​

APBC_COUNTER_CLK_SEL Offset:0x64

BitsFieldTypeResetDescription
31:16LOW_FREQ_STEPRW0x2DCGeneric Counter Step of Low Frequency
Under low frequency, this is the Generic Counter step value.
Default = 24 MHz / 32768 = 0x2DC
15:2RSVDRO0Reserved for future use
1FREQ_SW_SELRW0x0Generic Counter Frequency Software Select
Valid when Hardware Control is disabled (FREQ_HW_CTRL = 0).
0x0 = 24 MHz
0x1 = 32 kHz
0FREQ_HW_CTRLRW0x0Generic Counter Frequency Controlled by Hardware
0x0 = Software Control (uses FREQ_SW_SEL bit)
0x1 = Hardware Control (uses VCTCXO_EN signal)

If VCTCXO_EN = 1: Generic Counter clock frequency = 24 MHz
If VCTCXO_EN = 0: Generic Counter clock frequency = 32 kHz
CLOCK/RESET CONTROL REGISTER FOR TEMPERATURE SENSOR​

APBC_TSEN_CLK_RST Offset:0x6C

BitsFieldTypeResetDescription
31:3RSVDRO0Reserved for future use
2TSEN_RST_ENRW0x1Temperature Sensor Reset Enable
0 = Release Reset
1 = Reset
1TSEN_FCLK_ENRW0x0Temperature Sensor Function Clock Enable:
0x0 = Disable
0x1 = Enable
0TSEN_PCLK_ENRW0x0Temperature Sensor APB Clock Enable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR INTER-PROCESSOR COMMUNICATION AP TO AUDIO​

APBC_IPC_AP2AUD_CLK_RST Offset:0x90

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
All values = No clock
3RSVDRO0Reserved for future use
2RSTRW0x1Inter-Processor Communication (IPC) Reset Generation
This field resets both the APB and functional domain.
0 = Release Reset
1 = Reset
1FNCLKRW0x0IPC Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0IPC APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR CAN​

APBC_CANn_CLK_RST(n = 0~4) Offset:0xA0/0xA4/0x148/0x14C/0x150

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0CAN Functional Clock Select:
0x0 = 20 MHz (from PLL6)
0x1 = 40 MHz (from PLL6)
0x2 = 80 MHz (from PLL6)
0x3 = Reserved
3RSVDRO0Reserved for future use
2RSTRW0x1CAN Reset Generation
This field resets both APB and Functional domains.
0 = Release Reset
1 = Reset
1FNCLKRW0x0CAN Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0CAN APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable

PMUAP​

CSI CCIC2 CLOCK/RESET CONTROL REGISTER​

PMU_CSI_CCIC2_CLK_RES_CTRL Offset:0x24

BitsFieldTypeResetDescription
31CCIC3_PHY_CLK_SELRW0x0CCIC3 PHY Clock Select
0 = 102.4 MHz
1 = 51.2 MHz
30CCIC3_PHY_CLK_ENRW0x0CCIC3 PHY Clock Enable:
0x0 = Disable
0x1 = Enable
29CCIC3_PHY_CLK_RSTRW0x0CCIC3 PHY Clock Reset
This clock is also used for DPHY reset.
0 = Reset
1 = Release Reset
28:23RSVDRO0Reserved for future use
22:20CSI_FNC_CLK_DIVRW0x0CSI Controller Function Clock Divide Ratio
Formula:
csi_fnc_clk = CSI_FNC_CLK_DIV / (this field + 1)
19RSVDRO0Reserved for future use
18:16CSI_CLK_SELRW0x0CSI_CLK Source Select
0x0 = 491 MHz
0x1 = 409 MHz
0x2 = 614 MHz
0x3 = 819 MHz
0x4 = PLL2_DIV2 (no division)
0x5 = PLL2_DIV3 (no division)
0x6 = PLL2_DIV4 (no division)
0x7 = 1228 MHz (no division)
15CSI_CLK_FC_REQW1C0x0CSI Controller Function CLK FC Request
1 = Trigger frequency change
This field is cleared automatically when the FC completes.
14:8RSVDRO0Reserved for future use
7CCIC2_PHYCLK_SELRW0x0CCIC2 PHY Clock Select
0 = 102.4 MHz
1 = 51.2 MHz
6RSVDRO0Reserved for future use
5CCIC2_PHYCLK_ENRW0x0CCIC2 PHY Clock Enable:
0x0 = Disable
0x1 = Enable
4CSI_CLK_ENRW0x0CSI Controller Function Clock Enable:
0x0 = Disable
0x1 = Enable
3RSVDRO0Reserved for future use
2CCIC2_PHYCLK_RSTRW0x0CCIC2 PHY Clock Reset
This clock is also used for DPHY reset.
0 = Reset
1 = Release Reset
1CSI_CLK_RSTRW0x0Reset for CSI Controller Function Clock
0 = Reset
1 = Release Reset
0RSVDRO0Reserved for future use
ISP CLOCK/RESET CONTROL REGISTER​

PMU_ISP_CLK_RES_CTRL Offset:0x38

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30ISP_REPAIR_MEM_CTRL_TRIGW1C0x0ISP Repairable Memory Control Trigger
1 = Triggers ISP repairable memory control
This bit is hardware-cleared when the memory control repair is complete.
29ISP_REPAIR_MEM_CTRL_DONE_BYPASSRW0x0ISP Repairable Memory Control Done Bypass in ISP Hardware Mode
This field is valid only when the ISP is in hardware mode (ISP_HW_MODE = 1).
28:24RSVDRO0Reserved for future use
23ISP_CI_BUS_CLK_FC_REQW1C0x0ISP_CI Bus Clock FC Request
1 = Triggers a frequency change
This bit is hardware-cleared when the frequency change is complete.
22:21ISP_CI_BUS_CLK_SELRW0x0ISP_CI Bus Clock Select
0x0 = 409 MHz
0x1 = 491 MHz
0x2 = 614 MHz
0x3 = 245 MHz
20:18ISP_CI_BUS_CLK_DIVRW0x1ISP_CI Bus Clock Divide Ratio
Formula:
isp_ci_divided_bus_clk = isp_ci_bus_clk / (this field + 1)
17ISP_CI_BUS_CLK_ENRW0x0ISP_CI Bus Clock Enable:
This field enables the DMA clock for CCIC and ISP. It controls the first-level AXI clock gating for both modules. Note that second-level AXI clock gating for CCIC and ISP is controlled by separate registers.
0x0 = Disable
0x1 = Enable
16ISP_CI_BUS_CLK_RSTRW0x0ISP_CI Bus Clock Reset
0 = Reset
1 = Release Reset
15:0RSVDRO0Reserved for future use
LCD CLOCK/RESET CONTROL REGISTER1​

PMU_LCD_CLK_RES_CTRL1 Offset:0x44

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30LCD_PXCLK_FC_REQW1C0x0LCD PXCLK FC Request
Write 1 to trigger a frequency change.
This bit is hardware-cleared when the frequency change completes.
29LCD_MCLK_FC_REQW1C0x0LCD MCLK FC Request
Write 1 to trigger a frequency change.
This bit is hardware-cleared when the frequency change completes.
28V2D_FCLK_FC_REQW1C0x0V2D FCLK FC Request
Write 1 to trigger a frequency change.
This bit is hardware-cleared when the frequency change completes.
27V2D_SW_RSTRW0x0V2D Clock Domain Reset
0 = Reset
1 = Release Reset
26LCD_DSCCLK_FC_REQRW0x0LCD DSCCLK FC Request
Write 1 to trigger a frequency change.
This bit is hardware-cleared when the frequency change completes.
25:15RSVDRO0Reserved for future use
14DPHY_STOP_STATE_MUXRW0x0DPHY STOP State Mux Select
0x0 = dphy_stop_state synchronized to fclk
0x1 = dphy_stop_state not synchronized to fclk
13:12V2D_FCLK_SELRW0x0V2D FCLK Clock Source Select
0x0 = 491 MHz
0x1 = PLL2_DIV4
0x2 = 307 MHz
0x3 = 614 MHz
11:9V2D_FCLK_DIVRW0x2V2D FCLK Clock Divide Ratio
Formula:
V2D_FCLK = Clock Source / (this field + 1)
8V2D_FCLK_ENRW0x0V2D FCLK Enable:
0x0 = Disable
0x1 = Enable
7LCD_SW_SLEEPRW0x0LCD Software Sleep Mode
0 = Normal mode
1 = DSI PHY enters sleep mode
6LCD_HCLK_SWAP_CTRLRW0x0LCD HCLK Swap Control
Controls the HCLK source of LCD in D1P mode.
0x0 = System fabric clock for LCD HCLK source in D1P mode
0x1 = Bypass VCTXO clock for LCD HCLK source in D1P mode
5LCD_HCLK_ENRW0x0LCD HCLK Enable:
0x0 = Disable
0x1 = Enable
4LCD_SW_RSTRW0x0LCD Software Reset
0 = Reset
1 = Release Reset
3DSI_ESCCLK_RESETRW0x0DSI ESC Clock Reset
0 = Reset
2DSI_ESC_ENRW0x0DSI ESC Clock Enable:
0x0 = Disable
0x1 = Enable
1:0DSI_ESC_SELRW0x0DSI ESC Clock Select
0x0 = 51.2 MHz
0x1 = 47.26 MHz
0x2 = 25.6 MHz
0x3 = 76.8 MHz
LCD CLOCK/RESET CONTROL REGISTER2​

PMU_LCD_CLK_RES_CTRL2 Offset:0x4C

BitsFieldTypeResetDescription
31:29LCD_DSCCLK_SELRW0x0DSCCLK Clock Source Select
0x0 = 614 MHz
0x1 = 491 MHz
0x2 = PLL7_DIV5
0x3 = PLL6_DIV6
0x4 = PLL2_DIV7
0x5 = 409 MHz
0x6 = 51.2 MHz
0x7 = PLL2_DIV8
28RSVDRO0Reserved for future use
27:25LCD_DSCCLK_DIVRW0x0LCD DSCCLK Clock Divide Ratio
Formula:
LCD_DSCCLK = Clock Source / (this field + 1)
24LCD_PXCLK_BLANK_MSKRW0x1LCD PXCLK FC Wait BLANK Signal Mask
0 = Wait for LCD BLANK signal
1 = Do not wait for LCD BLANK signal
23:21LCD_PXCLK_SELRW0x0PXCLK Clock Source Select
0x0 = 614 MHz
0x1 = 491 MHz
0x2 = PLL7_DIV5
0x3 = PLL6_DIV6
0x4 = PLL2_DIV7
0x5 = PLL2_DIV4
0x6 = 51.2 MHz
0x7 = PLL2_DIV8
20RSVDRO0Reserved for future use
19:17LCD_PXCLK_DIVRW0x2LCD PXCLK Clock Divide Ratio
Formula:
LCD_PXCLK = Clock Source / (this field + 1)
16LCD_PXCLK_ENRW0x0LCD PXCLK Enable:
0x0 = Disable
0x1 = Enable
15LCD_DSCCLK_RESETRW0x0LCD DSCCLK Reset
0 = Reset
1 = Release Reset
14LCD_DSCCLK_ENRW0x0LCD DSCCLK Enable:
0x0 = Disable
0x1 = Enable
Note: This clock is also used for Camera AHB CLK. The Camera module can only enable this clock; never change the frequency.
13:10RSVDRO0Reserved for future use
9LCD_MCLK_RESETRW0x1LCD MCLK Reset
0 = Reset
1 = Release Reset
8RSVDRO0Reserved for future use
7:5LCD_MCLK_SELRW0x0MCLK Clock Source Select
0x0 = 409 MHz
0x1 = 491 MHz
0x2 = 614 MHz
0x3 = 307 MHz
All other values = Reserved (Do not use)
4:1LCD_MCLK_DIVRW0x2LCD MCLK Clock Divide Ratio
Formula:
LCD_MCLK = Clock Source / (this field + 1)
0LCD_MCLK_ENRW0x0LCD MCLK Enable:
0x0 = Disable
0x1 = Enable
Note: This clock is also used for Camera AHB CLK. The Camera module can only enable this clock; never change the frequency.
CCIC CLOCK/RESET CONTROL REGISTER​

PMU_CCIC_CLK_RES_CTRL Offset:0x50

BitsFieldTypeResetDescription
31CCIC_ISP_HCLK_SWAP_CTRLRW0x0CCIC ISP HCLK Swap Control
Controls the HCLK source of CCIC and ISP in D1P mode.
0x0 = System fabric clock for CCIC and ISP HCLK source in D1P mode
0x1 = Bypass VCTXO clock for CCIC and ISP HCLK source in D1P mode
30MASK_ISP_BLANK_CHECKRW0x0ISP FCLK FC Mask ISP Blank Check
Masks the ISP blank indication check for ISP FCLK frequency change.
1 = ISP FCLK FC will wait for blank signal
0 = Mask ISP blank check (do not wait)
29ISP_BLANK_CHECK_MODERW0x0ISP FCLK FC ISP Blank Check Mode
Selects the ISP blank mode for ISP FCLK frequency change.
1 = Use V-Blank flag
0 = Use H-Blank flag
28:26RSVDRO0Reserved for future use
25:23CCICI_CLK4X_SELRW0x00CLK4X Clock Source Select
0x0 = 491 MHz
0x1 = 409 MHz
0x2 = 614 MHz
0x3 = 819 MHz
0x4 = PLL2_DIV2 (no division)
0x5 = PLL2_DIV3 (no division)
0x6 = PLL2_DIV4 (no division)
0x7 = 1228 MHz (no division)
22:21RSVDRO0Reserved for future use
20:18CICIC_CLK4X_DIVRW0x1CI Function Clock Divide Ratio
Formula:
ci_fnc_clk = CI_FNC_CLK_DIV / (this field + 1)
17RSVDRO0Reserved for future use
16SC2_HCLK_FC_REQW1C0x0SC2_HCLK FC Request
Write 1 to trigger a frequency change.
This bit is hardware-cleared when the frequency change completes.
15CCIC_CLK4X_FC_REQW1C0x0CCIC Function CLK4X FC Request
Write 1 to trigger a frequency change.
This bit is hardware-cleared when the frequency change completes.
14:13RSVDRO0Reserved for future use
12:10SC2_HCLK_DIVRW0x1SC2 HCLK Clock Divide Ratio
Formula:
sc2_hclk = Clock Source / (this field + 1)
9:8SC2_HCLK_SELRW0x0SC2_HCLK Clock Source Select
0x0 = 307 MHz
0x1 = 409 MHz
0x2 = 491 MHz
0x3 = PLL2_DIV4
All other values = Reserved (Do not use)
7CCIC1_PHYCLK_SELRW0x0CCIC1 PHY Clock Select
0 = 102.4 MHz
1 = 51.2 MHz
6RSVDRO0Reserved for future use
5CCIC1_PHYCLK_ENRW0x0CCIC1 PHY Clock Enable:
0x0 = Disable
0x1 = Enable
4CCIC_CLK4X_ENRW0x0CMOS Camera Interface Controller Peripheral Clock Enable:
0x0 = Disable
0x1 = Enable
3SC2_HCLK_ENRW0x0SC2_HCLK Enable:
0x0 = Disable
0x1 = Enable
2CCIC1_PHYCLK_RSTRW0x0CCIC1 PHY Clock Reset
This clock is also used for DPHY reset.
0 = Reset
1 = Release Reset
1CCIC_CLK4X_RSTRW0x0CMOS Camera Interface Controller Peripheral Reset
0 = Reset
1 = Release Reset
0SC2_HCLK_RSTRW0x0SC2_HCLK Reset
0 = Reset
1 = Release Reset
SDH0 CLOCK/RESET CONTROL REGISTER​

PMU_SDH0_CLK_RES_CTRL Offset:0x54

BitsFieldTypeResetDescription
31:12RSVDRO0Reserved for future use
11SDH0_CLK_FC_REQW1C0x0SDH0 Clock Frequency Change Request
Write 1 to trigger the SDH0 clock divider update.
This bit is automatically cleared by hardware when the clock switch is complete.
10:8SDH0_CLK_DIVRW0x1SDH0 Clock Frequency Divisor
Range: 0x0 to 0x7
Formula:
SDH0_CLK = SDH0 Source Clock / (SDH0_CLK_DIV + 1)
7:5SDH0_CLK_SELRW0x0SDH0 Clock Source Select
0x0 = 409 MHz
0x1 = 614 MHz
0x2 = PLL2_DIV8
0x3 = PLL2_DIV5
0x4 = Reserved
0x5 = Reserved
0x6 = PLL1_DIVMMD
0x7 = Reserved
4SDH0_CLK_ENRW0x0SDH0 Peripheral Clock Enable:
0x0 = Disable
0x1 = Enable
3SDH_AXICLK_ENRW0x0All SDH AXI Clock Enable
Enables the AXI clock for all three SDH modules.
1 = AXI clock enabled
0 = AXI clock disabled
2RSVDRO0Reserved for future use
1SDH0_RSTRW0x0SDH0 Peripheral Reset
0 = Reset
1 = Release Reset
0SDH_AXI_RSTRW0x0All SDH AXI Reset
Performs an AXI reset for all three SDH modules.
0 = Reset
1 = Release Reset
SDH1 CLOCK/RESET CONTROL REGISTER​

PMU_SDH1_CLK_RES_CTRL Offset:0x58

BitsFieldTypeResetDescription
31:12RSVDRO0Reserved for future use
11SDH1_CLK_FC_REQW1C0x0SDH1 Clock Frequency Change Request
When this field is written as 1, it will force SDH1_CLK_DIV to work.
This bit is automatically cleared by hardware when the clock switch is complete.
10:8SDH1_CLK_DIVRW0x1SDH1 Clock Frequency Divisor
Range: 0 to 7
Formula:
SDH1_CLK = SDH1 Source Clock / (SDH1_CLK_DIV + 1)
7:5SDH1_CLK_SELRW0x0SDH1 Clock Source Select
0x0 = 409 MHz
0x1 = 614 MHz
0x2 = PLL2_DIV8
0x3 = PLL2_DIV5
0x4 = Reserved
0x5 = Reserved
0x6 = PLL1_DIVMMD
0x7 = Reserved
4SDH1_CLK_ENRW0x0SDH1 Peripheral Clock Enable:
0x0 = Disable
0x1 = Enable
3:2RSVDRO0Reserved for future use
1SDH1_RSTRW0x0SDH1 Peripheral Reset
0 = Reset
1 = Release Reset
0RSVDRO0Reserved for future use
USB CLOCK/RESET CONTROL REGISTER​

PMU_USB_CLK_RES_CTRL Offset:0x5C

BitsFieldTypeResetDescription
31VBUS_DLY_CNT_ENRW0x0VBUS Fall Edge Debounce Enable
30:23DLY_CNT_REGRW0x0Configures the debounce duration to detect the VBUS fall edge.
Valid only when VBUS_DLY_CNT_EN is set to 1.
22:20RSVDRO0Reserved for future use
19USB3_PORTD_PHY_RESETNRW0x0USB3 Port D PHY Reset
0 = Reset
1 = Release Reset
18USB3_PORTD_VCC_RESETNRW0x0USB3 Port D VCC Reset
0 = Reset
1 = Release Reset
17USB3_PORTD_AHB_RSTNRW0x0USB3 Port D AHB Reset
0 = Reset
1 = Release Reset
16USB3_PORTD_BUS_CLK_ENRW0x0USB3 Port D Bus Clock Enable:
0x0 = Disable
0x1 = Enable
15USB3_PORTC_PHY_RESETNRW0x0USB3 Port C PHY Reset
0 = Reset
1 = Release Reset
14USB3_PORTC_VCC_RESETNRW0x0USB3 Port C VCC Reset
0 = Reset
1 = Release Reset
13USB3_PORTC_AHB_RSTNRW0x0USB3 Port C AHB Reset
0 = Reset
1 = Release Reset
12USB3_PORTC_BUS_CLK_ENRW0x0USB3 Port C Bus Clock Enable:
0x0 = Disable
0x1 = Enable
11USB3_PORTB_PHY_RESETNRW0x0USB3 Port B PHY Reset
0 = Reset
1 = Release Reset
10USB3_PORTB_VCC_RESETNRW0x0USB3 Port B VCC Reset
0 = Reset
1 = Release Reset
9USB3_PORTB_AHB_RSTNRW0x0USB3 Port B AHB Reset
0 = Reset
1 = Release Reset
8USB3_PORTB_BUS_CLK_ENRW0x0USB3 Port B Bus Clock Enable:
0x0 = Disable
0x1 = Enable
7USB3_PORTA_PHY_RESETNRW0x0USB3 Port A PHY Reset
0 = Reset
1 = Release Reset
6USB3_PORTA_VCC_RESETNRW0x0USB3 Port A VCC Reset
0 = Reset
1 = Release Reset
5USB3_PORTA_AHB_RSTNRW0x0USB3 Port A AHB Reset
0 = Reset
1 = Release Reset
4USB3_PORTA_BUS_CLK_ENRW0x0USB3 Port A Bus Clock Enable:
0x0 = Disable
0x1 = Enable
3USB2_PORT_PHY_RESETNRW0x0USB2 Port PHY Reset
0 = Reset
1 = Release Reset
2USB2_PORT_VCC_RESETNRW0x0USB2 Port VCC Reset
0 = Reset
1 = Release Reset
1USB2_PORT_BUS_CLK_ENRW0x0USB2 Port Bus Clock Enable:
0x0 = Disable
0x1 = Enable
0USB2_PORT_AHB_RSTNRW0x0USB2 Port AHB Reset
0 = Reset
1 = Release Reset
QSPI CLOCK/RESET CONTROL REGISTER​

PMU_QSPI_CLK_RES_CTRL Offset:0x60

BitsFieldTypeResetDescription
31:13RSVDRO0Reserved for future use
12QSPI_CLK_FC_REQRWAC0x0QSPI Clock Frequency Change Request
Write 1 to force the QSPI_CLK_SEL setting to take effect.
This bit is automatically cleared by hardware when the clock switch is complete.
11:9QSPI_CLK_DIVRW0x7QSPI Clock Division Ratio
Formula:
QSPI Clock Freq = QSPI_CLK_SEL Freq / (QSPI_CLK_DIV + 1)
8:6QSPI_CLK_SELRW0x5QSPI Clock Source Select
0x0 = 409 MHz
0x1 = PLL2_DIV8
0x2 = 307 MHz
0x3 = 245 MHz
0x4 = Reserved
0x5 = PLL1_DIVMMD
0x6 = 491 MHz
0x7 = Reserved
5RSVDRO0Reserved for future use
4QSPI_CLK_ENRW0x1QSPI Function Clock Enable:
0x0 = Disable
0x1 = Enable
3QSPI_BUS_CLK_ENRW0x1QSPI Bus Clock Enable:
0x0 = Disable
0x1 = Enable
2RSVDRO0Reserved for future use
1QSPI_CLK_RSTRW0x1QSPI Clock Reset
0 = Reset
1 = Release Reset
0QSPI_BUS_RSTRW0x1QSPI Bus Clock Reset
0 = Reset
1 = Release Reset
DMA CLOCK/RESET CONTROL REGISTER​

PMU_DMA_CLK_RES_CTRL Offset:0x64

BitsFieldTypeResetDescription
31:4RSVDRO0Reserved for future use
3DMA_AXICLK_ENRW0x0DMA AXI Clock Enable:
0x0 = Disable
0x1 = Enable
2:1RSVDRO0Reserved for future use
0DMA_AXI_RSTRW0x0DMA AXI Reset
0 = Reset
1 = Release Reset
AES CLOCK/RESET CONTROL REGISTER​

PMU_AES_CLK_RES_CTRL Offset:0x68

BitsFieldTypeResetDescription
31OTP_KEY_SELRW0x0OTP key selection
30:26RSVDRO0Reserved for future use
25BCM_FAB_MAIN_CLK_GATERW0x0BCM Fabric Main Clock Gate
24BCM_FAB_WTM_CLK_GATERW0x0BCM Fabric WTM Clock Gate
23WTM_CLK_RSTN_TE200RW0x0TE200 WTM clock reset
22WTM_CLK_EN_TE200RW0x0High level active
21WTM_CLK_RSTN_ACRRW0x0ACR WTM clock reset
20WTM_CLK_EN_ACRRW0x0High level active
19WTM_CLK_RSTN_RNGRW0x0RNG WTM clock reset
18WTM_CLK_EN_RNGRW0x0High level active
17WTM_CLK_RSTN_BCMRW0x0BCM WTM clock reset
16WTM_CLK_EN_BCMRW0x0High level active
15:7RSVDRO0Reserved for future use
6WTM_CLK_SELRW0x0WTM Clock Source Select
0x0 = 204.8 MHz
0x1 = 102.4 MHz
5WTM_CLK_ENRW0x0WTM Clock Enable:
0x0 = Disable
0x1 = Enable
4WTM_RSTRW0x0WTM Clock Reset
0 = Reset
1 = Release Reset
3:0RSVDRO0Reserved for future use
MCB CLOCK/RESET CONTROL REGISTER​

PMU_MCB_CLK_RES_CTRL Offset:0x6C

BitsFieldTypeResetDescription
31:2RSVDRO0Reserved for future use
1ACLK_SW_RSTRW0x1MCB ACLK Port Reset
0 = Reset
1 = Release Reset
0DCLK_SW_RSTRW0x1MCB DCLK Domain Reset
0 = Reset
1 = Release Reset
VPU CLOCK/RESET CONTROL REGISTER​

PMU_VPU_CLK_RES_CTRL Offset:0xA4

BitsFieldTypeResetDescription
31:22RSVDRO0Reserved for future use
21VPU_CLK_FC_REQW1C0x0VPU Clock Frequency Change Request
Write 1 to trigger a frequency change.
This bit is automatically cleared by hardware when the change completes.
20:16RSVDRO0Reserved for future use
15:13VPU_CLK_DIVRW0x1VPU Function Clock Divide Ratio
Formula:
VPU_CLK = VPU_CLK_SEL / (Value + 1)
Note: Divider is only effective for clock sources 0, 1, 2, and 3.
12:10VPU_CLK_SELRW0x0VPU Function Clock Source Select
0x0 = 614 MHz
0x1 = 491 MHz
0x2 = 819 MHz
0x3 = 409 MHz
0x4 = 1228 MHz (No division applied)
0x5 = PLL2_DIV3 (No division applied)
0x6 = PLL2_DIV4 (No division applied)
0x7 = PLL2_DIV5 (No division applied)
9:4RSVDRO0Reserved for future use
3VPU_CLK_ENRW0x0VPU Function Clock Enable:
0x0 = Disable
0x1 = Enable
2:1RSVDRO0Reserved for future use
0VPU_RSTRW0x0VPU Reset
0 = Reset
1 = Release Reset
DTC CLOCK/RESET CONTROL REGISTER​

PMU_DTC_CLK_RES_CTRL Offset:0xAC

BitsFieldTypeResetDescription
31:4RSVDRO0Reserved for future use
3DTC_AXICLK_ENRW0x0DTC AXI Clock Enable:
0x0 = Disable
0x1 = Enable
2:1RSVDRO0Reserved for future use
0DTC_AXI_RSTRW0x0DTC AXI Reset
0 = Reset
1 = Release Reset
GPU CLOCK/RESET CONTROL REGISTER​

PMU_GPU_CLK_RES_CTRL Offset:0xCC

BitsFieldTypeResetDescription
31:21RSVDRO0Reserved for future use
20:18GPU_CLK_SELRW0x0GPU Clock Source Select
0x0 = 614 MHz
0x1 = 491 MHz
0x2 = 819 MHz
0x3 = 409 MHz
0x4 = 1228 MHz (No division applied)
0x5 = PLL2_DIV3 (No division applied)
0x6 = PLL2_DIV4 (No division applied)
0x7 = PLL2_DIV5 (No division applied)
17:16RSVDRO0Reserved for future use
15GPU_FNC_FC_REQW1C0x0GPU Function Clock Frequency Change Request
Write 1 to trigger a frequency change.
This bit is automatically cleared by hardware when the change completes.
14:12GPU_CLK_DIVRW0x1GPU Function Clock Divider
Formula:
GPU_FNC_CLK = GPU_CLK_SEL / (Value + 1)
Note: Divider is only effective for clock sources 0, 1, 2, and 3.
11:5RSVDRO0Reserved for future use
4GPU_CLK_ENRW0x0GPU Clock Enable:
0x0 = Disable
0x1 = Enable
3:2RSVDRO0Reserved for future use
1GPU_RSTRW0x0GPU Reset
0 = Reset
1 = Release Reset
0RSVDRO0Reserved for future use
SDH2 CLOCK/RESET CONTROL REGISTER​

PMUA_SDH2_CLK_RES_CTRL Offset:0xE0

BitsFieldTypeResetDescription
31:12RSVDRO0Reserved for future use
11SDH2_CLK_FC_REQW1C0x0SDH2 Clock Frequency Change Request
Write 1 to force the SDH2_CLK_DIV to take effect.
This bit is automatically cleared by hardware when the clock switch is complete.
10:8SDH2_CLK_DIVRW0x1SDH2 Clock Frequency Divisor
Range: 0 - 7
Formula:
SDH2_CLK = SDH2_Source_CLK / (Value + 1)
7:5SDH2_CLK_SELRW0x0SDH2 Clock Source Select
0x0 = 409 MHz
0x1 = 614 MHz
0x2 = PLL2_DIV8
0x3 = 819 MHz
0x4 = Reserved
0x5 = Reserved
0x6 = PLL1_DIVMMD
0x7 = Reserved
4SDH2_CLK_ENRW0x0SDH2 Peripheral Clock Enable:
0x0 = Disable
0x1 = Enable
3:2RSVDRO0Reserved for future use
1SDH2_RSTRW0x0SDH2 Peripheral Reset
0 = Reset
1 = Release Reset
0RSVDRO0Reserved for future use
MEMORY CONTROLLER AHB REGISTER​

PMUA_MC_CTRL Offset:0xE8

BitsFieldTypeResetDescription
31DFC_D1P_BLOCKRW0x01: block DFC during D1P
0: enable DFC during D1P
30DDR_DPHY_PURW0x1DDR DPHY PU control. Don't change, it should be always high.
in dove, it could set to 0 and use ckphy_fc_ctrl.PU_PHY_A/B to enable half phy.
29MC_CLK_GATE_BYPSRW0x01: bypass MCK_root clock gating during low power state
0: no bypass, MCK_root gated during low power state for saving power
28:26MC_DEBUG_4_2RW0x0debug bit, not set in normal working!
mc_debug [4] DOVE_A0 RESET_MC DEBUG, flush_en, flush MC when execute table
mc_debug [3] DOVE_A0 RESET_MC DEBUG, reset MC during D1/D1PP with csysreq/ack, work with flush_en
mc_debug [2] DOVE_A0 RESET_MC DEBUG, when reset MC also reset digphy, require re-training and program digphy
25BYPS_DEASS_PWROKRW0x0debug bit
1: bypass deassert PwrOk in main pmu when pll off
0: deassert PwrOk in main pmu before pll off
24MC_INIT_MODE_DISRW0x0debug bit, not set in normal working!
1: disable MC initial mode to MC table after LP, if set MC will not initial after LP
0: MC initial mode controlled by hardware enable after LP and clear after initial done if MC is reset during LP
23:20MC_DEBUG2_HRW0x0debug bit, not set in normal working!
mc_debug2 [7] DOVE_A0 D1PP_DCLK_SWITCH_EN, change dclk to ext for save power! NOTE, ckext is stop in LowPower, cant dfc to ckext and go to lowpower mode
mc_debug2 [6] DOVE_A0 DDR_PHY_PD_EN, power down DDR PHY in D1PP for save power!
mc_debug2 [5] reserved
mc_debug2 [4] DOVE_A0 RESET_MC DEBUG, flush_dis, do not flush MC when execute table, override by flush_en
19:18RSVDRO0Reserved for future use
17MC_DEASS_PWROKRW0x01: deassert PwrOk for MC PHY,
the bit would be cleared automatically
16MC_ASS_PWROKRW0x01: assert PwrOk for MC PHY,
the bit would be cleared automatically
15MC_LP_RESET_EN0RW0x0debug bit, not set in normal working! Memory Controller reset in D1 state
14:8MC_D2_INIT_ENTRYRW0x10Memory Controller initial entry by MC table after D2 exit, please use 0x10 and prepare the table
7:4MC_DEBUG2_LRW0mc_debug2 [3] DOVE_A0 RESET_MC DEBUG, reset MC during D1 with pu_ckphy, work with flush_en
mc_debug2 [2] DOVE_A0 RESET_MC DEBUG, reset MC during D2 if disable powerdown, work with flush_en
3:2RSVDRO0Reserved for future use
1MC_AHBCLK_ENRW0x0Memory Controller AHB Clock Enable:
0x0 = Disable
0x1 = Enable
0MC_HCLK_RSTRW0x0Memory Controller HCLK Reset
0 = Reset
1 = Release Reset
PMU_TOP_DCLK_CTRL REGISTER​

PMU_TOP_DCLK_CTRL Offset:0x158

BitsFieldTypeResetDescription
31:9RSVDRO0Reserved for future use
8TOP_DCLK_FC_REQW1C0x0TOP_DCLK Frequency Change Request
1 = Force TOP_DCLK_SEL to take effect
This field is automatically cleared by hardware when clock switch is done
7:5TOP_DCLK_DIVRW0x0TOP_DCLK_DIV
TOP_DCLK = clock source / (this field + 1)
Only for clock sources (TOP_DCLK_SEL == 0/1/2/3); for other clock sources, DIV is 1
4:2TOP_DCLK_SELRW0x0Top DCLK Clock Select
0x0 = 307MHz
0x1 = 409MHz
0x2 = pll3_div4
0x3 = pll6_div5
0x4 = pll7_div4 (no divided)
0x5 = pll6_div4 (no divided)
0x6 = pll7_div3 (no divided)
0x7 = pll6_div3 (no divided)
1TOP_DCLK_ENRW0x1Top DCLK Enable:
0x0 = Disable
0x1 = Enable
0RSVDRO0Reserved for future use
AP CLOCK CONTROL REGISTER2​

PMU_CC2_AP This register is used to trigger CPU core reset.

  1. Core power-on reset signals initialize all the processor logic, including CPU Debug and breakpoint and watchpoint logic in the processor power domains.
  2. Core software reset initializes the processor logic in the processor power domains, not including the debug, breakpoint and watchpoint logic.
  3. At the CORE level, these signals reset only the debug, and breakpoint and watchpoint logic in the processor power domain. At the level, these signals also reset the debug logic for each processor, which is in the debug power domain.

Offset:0x100

BitsFieldTypeResetDescription
31:30RSVDRO0Reserved for future use
29MPSUB_DBG_RSTRW0x0 Debug Reset
This field is used to reset the debug/Coresight logic, including core dbg logic.
0 = Release Reset
1 = Reset
28C1_MPSUB_SW_RSTRW0x0 Reset
This field is used to reset the logic except debug/Coresight logic.
0 = Release Reset
1 = Reset
27RSVDRO0Reserved for future use
26CPU7_SW_RSTRW0x0CPU7 Core Software Reset
0 = Release Reset
1 = Reset
25CPU7_POR_RSTRW0x0CPU7 Core Power-On Reset
This field is used to reset CPU7 all logic, including debug logic.
0 = Release Reset
1 = Reset
24RSVDRO0Reserved for future use
23CPU6_SW_RSTRW0x0CPU6 Core Software Reset
This field is used to reset CPU6 core logic only.
0 = Release Reset
1 = Reset
22CPU6_POR_RSTRW0x0CPU6 Core Power-On Reset
This field is used to reset CPU6 all logic, including debug logic.
0 = Release Reset
1 = Reset
21RSVDRO0Reserved for future use
20CPU5_SW_RSTRW0x0CPU5 Core Software Reset
This field is used to reset CPU5 core logic only.
0 = Release Reset
1 = Reset
19CPU5_POR_RSTRW0x0CPU5 Core Power-On Reset
This field is used to reset CPU5 all logic, including debug logic.
0 = Release Reset
1 = Reset
18RSVDRO0Reserved for future use
17CPU4_SW_RSTRW0x0CPU4 Core Software Reset
This field is used to reset CPU4 core logic only.
0 = Release Reset
1 = Reset
16CPU4_POR_RSTRW0x0CPU4 Core Power-On Reset
This field is used to reset CPU4 all logic including debug logic.
0 = Release Reset
1 = Reset
15:13RSVDRO0Reserved for future use
12C0_MPSUB_SW_RSTRW0x0 Reset
This field is used to reset the logic except debug/Coresight logic.
0 = Release Reset
1 = Reset
11RSVDRO0Reserved for future use
10CPU3_SW_RSTRW0x0CPU3 Core Software Reset
0 = Release Reset
1 = Reset
9CPU3_POR_RSTRW0x0CPU3 Core Power-On Reset
This field is used to reset CPU3 all logic, including debug logic.
0 = Release Reset
1 = Reset
8RSVDRO0Reserved for future use
7CPU2_SW_RSTRW0x0CPU2 Core Software Reset
This field is used to reset CPU2 core logic only.
0 = Release Reset
1 = Reset
6CPU2_POR_RSTRW0x0CPU2 Core Power-On Reset
This field is used to reset CPU2 all logic, including debug logic.
0 = Release Reset
1 = Reset
5RSVDRO0Reserved for future use
4CPU1_SW_RSTRW0x0CPU1 Core Software Reset
This field is used to reset CPU1 core logic only.
0 = Release Reset
1 = Reset
3CPU1_POR_RSTRW0x0CPU1 Core Power-On Reset
This field is used to reset CPU1 all logic, including debug logic.
0 = Release Reset
1 = Reset
2RSVDRO0Reserved for future use
1CPU0_SW_RSTRW0x0CPU0 Core Software Reset
This field is used to reset CPU0 core logic only.
0 = Release Reset
1 = Reset
0CPU0_POR_RSTRW0x0CPU0 Core Power-On Reset
This field is used to reset CPU0 all logic including debug logic.
0 = Release Reset
1 = Reset
TRACE CLOCK CONTROL REGISTER​

TRACE_CONFIG Offset:0x108

BitsFieldTypeResetDescription
31:22RSVDRO0Reserved for future use
21:19PCLKDBG_DIVRW0x1Clock Divider Selection for PCLKDBG.
PCLKDBG = ATCLK / (this field + 1)
18:17DBG_CLK_SELRW0x0Internal Trace Clock Source Select
0x0 = 307 MHz
0x1 = 409 MHz
Note that the debug clock is generated based on ATCLK.
16SWRSTRW0x1Software Reset
This field is used to reset all debug logic, low assert
15TRACE_CLK_FC_REQW1C0x0Trace Clock Frequency Change Request
1 = Force TRACE_CLK_DIV to take effect
This field is automatically cleared by hardware when clock switch is done
14:12RSVDRO0Reserved for future use
11TPIU_CLK_SELRW0x0TPIU Clock Selection
Select TPIU use internal clock or external input clock from PAD, default will use the clock from internal
10:8TRACE_CLK_DIVRW0x1Trace Clock Frequency Divisor
0-7 = TRACE_CLK = TRACE source clock / (TRACE_CLK_DIV + 1)
7RSVDRO0Reserved for future use
6TRACE_CLK_SELRW0x0Internal Trace Clock Source Select
0x0 = 307 MHz
0x1 = 409 MHz
5DBG_CLK_FC_REQW1C0x0Debug Clock Frequency Change Request
1 = Force DBG_CLK_DIV to operate
This field is automatically cleared by hardware when clock switch is done
4TRACE_CLK_ENRW0x1Trace Clock Enable:
0x0 = Disable
0x1 = Enable
3DBGCLK_ENRW0x1Debug Clock Enable (including ATCLK and PCLKDBG):
0x0 = Disable
0x1 = Enable
2:0DBGCLK_DIVRW0x3Clock Divider Selection for ATCLK
ATCLK = (debug clock selection in TRACE_CONFIG[18:17]) / (this field + 1)
USB PHY TEST REGISTER​

UCIE_CTRL Offset:0x11C

BitsFieldTypeResetDescription
31:25UCIE_BGR_I2C_DEV_IDRW0x0UCIE BGR IP I2C device ID
24UCIE_BGR_I2C_MODERW0x0UCIE BGR IP I2C mode
23:17UCIE_EW_I2C_DEV_IDRW0x0UCIE EW IP I2C device ID
16UCIE_EW_I2C_MODERW0x0UCIE EW IP I2C mode
15UCIE_BGR_J2A_EN_ONRW0x01 = Enable UCIE_BGR IP JTAG interface function
14:9RSVDRO0Reserved for future use
8CFG_UCIE_SBCLK_ENRW0x0SBCLK gate enable
7RSVDRO0Reserved for future use
6:4CFG_UCIE_ACLK_SELRW0x0UCIE ACLK clock select
0x0 = 307MHz
0x1 = 409MHz
0x2 = pll3_div4
0x3 = pll6_div5
0x4 = pll7_div4
0x5 = pll6_div4
All other values = Reserved, do not use
3CFG_UCIE_MON_RST_NRW0x0UCIE monitor reset
0 = Reset
1 = Reset Release
2CFG_UCIE_HOT_RST_NRW0x0UCIE IP hot reset signal
0 = Reset
1 = Reset Release
1CFG_UCIE_IP_RST_NRW0x0UCIE IP reset signal
0 = Reset
1 = Reset Release
0CFG_UCIE_IP_ACLK_ENRW0x0UCIE IP ACLK enable signal
0 = Disable
1 = Enable
AUDIO CLOCK RESET ENABLE REGISTER​

PMU_AUDIO_CLK_RES_CTRL Offset:0x14C

BitsFieldTypeResetDescription
31AUDIO_PWR_STATUS_1RO0x1Audio SD domain status
1 = Audio PMU is in power-on status
0 = Audio PMU is in power-off status
30USE_SOFT_RSTRW0x0This bit forces audio to use soft reset
29AUDIO_AUTO_POWER_ON_OFF_TRIGGER_IN_HARDWARE_MODERW0x1Audio Auto Power On/Off Trigger in Hardware Mode
1 = Triggers request to power up the Audio power island
0 = Triggers request to power down Audio power
28AP_POWER_CTL_AUDIO_AUTHORW0x1AP Power Control Audio Authority
1 = AP can control Audio power now
0 = AP cannot control Audio power, and Audio PMU controls the audio power switch.
27:24RSVDRO0Reserved for future use
23AUDIO_PWR_STATUSRO0x1Status for Audio PMU
0 = Audio PMU is in power-off status
1 = Audio PMU is in power-on status
22:20RSVDRO0Reserved for future use
19LOG_ENRW0x0This bit enables or disables debug information recording, such as PC value and bus status.
0 = Disable
1 = Enable
18ADSP_ENRW0x00 = Hold DSP wait
1 = DSP active run
17:16RSVDRO0Reserved for future use
15AUDIO_FC_REQW1C0x0Audio island main clock FC Request
1 = Triggers a frequency change
This field is hardware cleared when the frequency change is done.
14FORCE_AUD_PWR_OFFRW0x01 = Force audio power off
0 = Do not force audio power off
13FORCE_AUD_PWR_ONRW0x01 = Force audio power on
0 = Do not force audio power on
12AUDIO_CLK_ENRW0x0Audio clock enable
1 = Enable
11CUR_PWR_MSTRO0x0Indicator bit for audio power control authority
1 = AP controls audio power switch
0 = Audio PMU controls audio power switch
10AUDIO_HW_CKG_BYPASSRW0x0Audio always-on domain reset; this bit should always be set to 1 after silicon power-up
9:7AUDIO_CLK_SELRW0x0Clock select control for audio main clock.
0x0 = 245MHz
0x1 = 307MHz
0x2 = 491MHz
0x3 = 409MHz
All other values = Reserved, do not use
6:4AUDIO_CLK_DIVRW0x0Clock divider control for audio main clock
Audio main clk = selected clk / (AUDIO_CLK_DIV + 1)
3AUDIO_APMU_RESETRW0x0Audio APMU reset; this bit should always be set to 1 after silicon power-up
0 = Reset
1 = Reset Release
2AUD_MCU_CORE_RESETRW0x0Soft AUD_MCU core reset
0 = Reset
1 = Reset Release
1RSVDRO0Reserved for future use
0AUDIO_SYS_RESETRW0x0Soft audio island system reset
0 = Reset
1 = Reset Release
LCD CLOCK/RESET CONTROL REGISTER3​

PMU_LCD_CLK_RES_CTRL3 Offset:0x26C

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30DSI4LN2_LCD_PXCLK_FC_REQW1C0x0DSI4LN2_LCD PXCLK FC Request
Write 1 to trigger a frequency change. This field is hardware cleared when the frequency change completes.
29DSI4LN2_LCD_MCLK_FC_REQW1C0x0DSI4LN2_LCD MCLK FC Request
Write 1 to trigger a frequency change. This field is hardware cleared when the frequency change completes.
28:27RSVDRO0Reserved for future use
26DSI4LN2_LCD_DSCCLK_FC_REQRW0x0DSI4LN2_LCD DSCCLK FC Request
Write 1 to trigger a frequency change. This field is hardware cleared when the frequency change completes.
25:8RSVDRO0Reserved for future use
7DSI4LN2_LCD_SW_SLEEPRW0x0DSI4LN2_LCD SW SLEEP
0 = normal mode
1 = dsi phy enter sleep mode
6:5RSVDRO0Reserved for future use
4DSI4LN2_LCD_SW_RSTRW0x0DSI4LN2_LCD Software Reset
0 = Reset
1 = Reset Release
3DSI4LN2_ESCCLK_RESETRW0x0DSI4LN2 ESC Clock Reset
0 = Reset
2DSI4LN2_DSI_ESC_ENRW0x0DSI4LN2 ESC Clock Enable:
0x0 = Disable
0x1 = Enable
1:0DSI4LN2_DSI_ESC_SELRW0x0DSI4LN2_ESC Clock Select
0x0 = 51.2 MHz
0x1 = 47.26 MHz
0x2 = 25.6 MHz
0x3 = 76.8 MHz
LCD CLOCK/RESET CONTROL REGISTER4​

PMU_LCD_CLK_RST_CTRL4 Offset:0x270

BitsFieldTypeResetDescription
31:29DSI4LN2_LCD_DSCCLK_SELRW0x0DSI4LN2_LCD DSCCLK Clock Source Select
0x0 = 614MHz
0x1 = 491MHz
0x2 = pll7_div5
0x3 = pll6_div6
0x4 = pll2_div7
0x5 = 409MHz
0x6 = 51.2MHz
0x7 = reserved
28RSVDRO0Reserved for future use
27:25DSI4LN2_LCD_DSCCLK_DIVRW0x0DSI4LN2_LCD DSCCLK Clock Divide Ratio
LCD_DSCCLK = clock source / (this field + 1)
24DSI4LN2_LCD_PXCLK_BLANK_MSKRW0x1DSI4LN2_LCD PXCLK FC wait BLANK signal mask
0 = wait LCD BLANK signal
1 = not wait LCD BLANK signal
23:21DSI4LN2_LCD_PXCLK_SELRW0x0DSI4LN2_LCD PXCLK Clock Source Select
0x0 = 614MHz
0x1 = 491MHz
0x2 = pll7_div5
0x3 = pll6_div6
0x4 = pll2_div7
0x5 = pll2_div4
0x6 = 51.2MHz
0x7 = pll2_div8
20RSVDRO0Reserved for future use
19:17DSI4LN2_LCD_PXCLK_DIVRW0x2DSI4LN2_LCD PXCLK Clock Divide Ratio
LCD_PXCLK = clock source / (this field + 1)
16DSI4LN2_LCD_PXCLK_ENRW0x0DSI4LN2_LCD PXCLK Enable:
0x0 = Disable
0x1 = Enable
15DSI4LN2_LCD_DSCCLK_RESETRW0x0DSI4LN2_LCD DSCCLK Reset
0 = Reset
1 = Reset Release
14DSI4LN2_LCD_DSCCLK_ENRW0x0DSI4LN2_LCD DSCCLK Enable:
0x0 = Disable
0x1 = Enable
Note: this clock is also used for camera ahb clk, camera can only enable this clk, never change the freq !!!
13:10RSVDRO0Reserved for future use
9DSI4LN2_LCD_MCLK_RESETRW0x1DSI4LN2_LCD MCLK Reset
0 = Reset
1 = Reset Release
8RSVDRO0Reserved for future use
7:5DSI4LN2_LCD_MCLK_SELRW0x0DSI4LN2_LCD MCLK Clock Source Select
0x0 = 409MHz
0x1 = 491MHz
0x2 = 614MHz
0x3 = 307MHz
All other values = Reserved, do not use
4:1DSI4LN2_LCD_MCLK_DIVRW0x2DSI4LN2_LCD MCLK Clock Divide Ratio
DSI4LN2_LCD_MCLK = clock source / (this field + 1)
0DSI4LN2_LCD_MCLK_ENRW0x0DSI4LN2_LCD MCLK Enable:
0x0 = Disable
0x1 = Enable
Note: this clock is also used for camera ahb clk, camera can only enable this clk, never change the freq !!!
UFS CLOCK/RESET CONTROL REGISTER​

PMU_UFS_CLK_RST_CTRL Offset:0x268

BitsFieldTypeResetDescription
31:9RSVDRO0Reserved for future use
8UFS_ACLK_FC_REQW1C0x0UFS ACLK FC Request
Write 1 to trigger a frequency change. This field is hardware cleared when the frequency change completes.
7:5UFS_ACLK_DIVRW0x0UFS ACLK Clock Divide Ratio
Fufs_aclk = clock source / (this field + 1)
4:2UFS_ACLK_SELRW0x0UFS ACLK Clock Select
0x0 = 491MHz
0x1 = 409MHz
0x2 = pll2_div6
0x3 = pll2_div5
All other values = Reserved, do not use
1UFS_ACLK_ENRW0x0UFS ACLK Clock Enable:
0 = Disable
1 = Enable
0UFS_ACLK_RSTRW0x0UFS ACLK Clock Reset
This reset is UFS global reset.
0 = Reset
1 = Reset Release
LCD CLOCK/RESET CONTROL REGISTER5​

PMU_LCD_CLK_RST_CTRL5 Offset:0x274

BitsFieldTypeResetDescription
31DPU_ACLK_REQRW0x0Request
Write 1 to trigger a frequency change. This field is hardware cleared when the frequency change completes.
30DSI4LN2_DPU_ACLK_REQRW0x0Request
Write 1 to trigger a frequency change. This field is hardware cleared when the frequency change completes.
29:23RSVDRO0Reserved for future use
22:20DPU_ACLK_SELRW0x0DPU ACLK clock source select
0x0 = 409MHz
0x1 = 491MHz
0x2 = 614MHz
0x3 = 307MHz
0x4 = pll2_div4
All other values = Reserved, do not use
19:17DPU_ACLK_DIVRW0x0LCD_DPU_ACLK_DIV = clock source / (this field + 1)
16DPU_ACLK_ENRW0x0CLK Enable:
0 = Disable
1 = Enable
15DPU_ACLK_RSTNRW0x0Reset
0 = Reset
1 = Reset Release
14:8RSVDRO0Reserved for future use
7:5DSI4LN2_DPU_ACLK_SELRW0x0DSI4LN2 DPU ACLK clock source select
0x0 = 409MHz
0x1 = 491MHz
0x2 = 614MHz
0x3 = 307MHz
0x4 = pll2_div4
All other values = Reserved, do not use
4:2DSI4LN2_DPU_ACLK_DIVRW0x0DSI4LN2_LCD_DPU_ACLK_DIV = clock source / (this field + 1)
1DSI4LN2_DPU_ACLK_ENRW0x0CLK Enable:
0 = Disable
1 = Enable
0DSI4LN2_DPU_ACLK_RSTNRW0x0Reset
0 = Reset
1 = Reset Release
LCD EDP CONTROL REGISTER​

PMU_LCD_EDP_CTRL Offset:0x23C

BitsFieldTypeResetDescription
31:19RSVDRO0Reserved for future use
18EDP1_PIXCLK_SELRW0x0eDP1 PIXCLK selection
0x0 = Use dsi4ln2_lcd_pxclk
0x1 = Use pixclk from eDP1 PLL
17EDP1_PCLK_ENRW0x0eDP1 APB PCLK enable:
0 = Disable
1 = Enable
16EDP1_PRSTNRW0x0eDP1 APB RESETN
0 = Reset
1 = Reset Release
15:3RSVDRO0Reserved for future use
2EDP0_PIXCLK_SELRW0x0eDP0 PIXCLK selection
0x0 = Use lcd_pxclk
0x1 = Use pixclk from eDP0 PLL
1EDP0_PCLK_ENRW0x0eDP0 APB PCLK enable:
0 = Disable
1 = Enable
0EDP0_PRSTNRW0x0eDP0 APB RESETN
0 = Reset
1 = Reset Release
CCI550 CLOCK CONTROL REGISTER​

PMU_CCI_CLK_CTRL Offset:0x300

BitsFieldTypeResetDescription
31:17RSVDRO0Reserved for future use
16MASK_DRAGON_ADB400_CCI_SIDE_IDLERW0x0Mask dragon ADB400 CCI side idle flag for cci_idle_clk_off_req
1 = Mask
0 = Unmask
15CCI_CLK_SMOOTH_MUX_DISRW0x0CCI clock smoothMUX disable
0 = CCI clock smoothMUX enable; it will HW switch to VCXO clock when CPU enters M2 and GPU shuts down
1 = CCI clock smoothMUX disable; it only selects the clock from cci_clock_gen; when CPU enters M2 and GPU shuts down, the CCI clock is gated.
14CCI_CLKEN_BY_INT_APRW0x0CCI clock can also be enabled by sys_int_ap[127:0]
0x1 = Enable this function
If this bit is 0x0, then the CCI clock is still only controlled by the status of CPU clusters and GPU
13CCI550_CLKGEN_AUTO_CG_ENRW0x0CCI550 clock generator working-clock automatic gating control
0x0 = CCI550 clock generator working-clock automatic gating is disabled and the clock is free-running
0x1 = CCI550 clock generator working-clock automatic gating is enabled
12CCI550_FC_REQRW0x0CCI550 frequency change request
When frequency change is done, this bit is automatically cleared by hardware
11:10RSVDRO0Reserved for future use
9:8CCI550_BIU_CLK_DIVRW0x1Clock Divider Selection for CCI550 AXI_M0 port to fabric.
ACLK_M0 = ACLKM1 / (this field + 1)
7:3RSVDRO0Reserved for future use
2:0CCI550_PLLSELRW0x0CCI550 Clock Selection
0x0 = 245MHz
0x1 = 409MHz
0x2 = 614MHz
0x3 = 819MHz
0x4 = pll7_div3 (no divided)
0x5 = pll2_div3 (no divided)
0x6 = 1228MHz (no divided)
0x7 = pll7_div2 (no divided)
AP ACLK CONTROL REGISTER​

PMUA_ACLK_CTRL Offset:0x388

BitsFieldTypeResetDescription
31:5RSVDRO0Reserved for future use
4ACLK_FC_REQRW0x0ACLK frequency change request
1 = Enable ACLK FC.
When frequency change is done, hardware will automatically clear this bit.
3RSVDRO0Reserved for future use
2:1ACLK_DIVRW0x0ACLK Divider
Formula:
ACLK = ACLK_SEL / (ACLK_DIV + 1)
0ACLK_SELRW0x0ACLK Source Selection
0x0 = 307MHz
0x1 = 409MHz
AP CPU CLUSTER0 CLK CONTROL REGISTER​

PMUA_CPU_C0_CLK_CTRL Offset:0x38C

BitsFieldTypeResetDescription
31:13RSVDRO0Reserved for future use
12C0_CLK_FC_REQRW0x0CPU Cluster0 Clock Frequency Change Request
1 = Enable clock frequency change.
When frequency change is done, hardware will automatically clear this bit.
11:6RSVDRO0Reserved for future use
5:3C0_CORE_CLK_DIVRW0x0Clock Divider Selection for C0_CORE_CLK
Formula: C0_CORE_CLK = Clock Selection / (this field + 1)
Note: Only used when C0_CLK_SEL is 0, 1, 2, or 3.
2:0C0_CLK_SELRW0x0C0 Clock Selection
0x0 = 819MHz
0x1 = 491MHz
0x2 = 614MHz
0x3 = pll2_div3
0x4 = pll3_div2 (no divided)
0x5 = 1228MHz (no divided)
0x6 = pll2_div2 (no divided)
0x7 = pll3_div1 (no divided)
AP CPU CLUSTER1 CLK CONTROL REGISTER​

PMUA_CPU_C1_CLK_CTRL Offset:0x390

BitsFieldTypeResetDescription
31:14RSVDRO0Reserved for future use
13C1_SRC7_PLL_SELRW0x0C1 Source7 PLL Selection
0x0 = pll4_div1
0x1 = pll3_div1
12C1_CLK_FC_REQRW0x0CPU Cluster1 Clock Frequency Change Request
1 = Enable clock frequency change.
When frequency change is done, hardware will automatically clear this bit.
11:6RSVDRO0Reserved for future use
5:3C1_PCLK_DIVRW0x0Clock Divider Selection for C1_PCLK
Formula: C1_PCLK = Clock Selection / (this field + 1)
Note: Only used when C1_CLK_SEL is 0, 1, 2, or 3.
2:0C1_CLK_SELRW0x0C1 Clock Selection
0x0 = 819MHz
0x1 = 491MHz
0x2 = 614MHz
0x3 = pll2_div3
0x4 = pll4_div2 (no divided)
0x5 = 1228MHz (no divided)
0x6 = pll2_div2 (no divided)
0x7 = pll4_div1 or pll3_div1 (selected by bit 13, no divided)
AP CPU CLUSTER2 CLK CONTROL REGISTER​

PMUA_CPU_C2_CLK_CTRL Offset:0x394

BitsFieldTypeResetDescription
31:13RSVDRO0Reserved for future use
12C2_CLK_FC_REQRW0x0CPU Cluster2 Clock Frequency Change Request
1 = Enable clock frequency change.
When frequency change is done, hardware will automatically clear this bit.
11:6RSVDRO0Reserved for future use
5:3C2_PCLK_DIVRW0x0Clock Divider Selection for C2_PCLK
Formula: C2_PCLK = Clock Selection / (this field + 1)
Note: Only used when C2_CLK_SEL is 0, 1, 2, or 3.
2:0C2_CLK_SELRW0x0C2 Clock Selection
0x0 = 819MHz
0x1 = 491MHz
0x2 = 614MHz
0x3 = pll2_div3
0x4 = pll5_div2 (no divided)
0x5 = 1228MHz (no divided)
0x6 = pll2_div2 (no divided)
0x7 = pll5_div1 (no divided)
AP CPU CLUSTER3 CLK CONTROL REGISTER​

PMUA_CPU_C3_CLK_CTRL Offset:0x208

BitsFieldTypeResetDescription
31:14RSVDRO0Reserved for future use
13C3_SRC7_PLL_SELRW0x0C3 Source7 PLL Selection
0x0 = pll8_div1
0x1 = pll5_div1
12C3_CLK_FC_REQRW0x0CPU Cluster3 Clock Frequency Change Request
1 = Enable clock frequency change.
When frequency change is done, hardware will automatically clear this bit.
11:6RSVDRO0Reserved for future use
5:3C3_PCLK_DIVRW0x0Clock Divider Selection for C3_PCLK
Formula: C3_PCLK = Clock Selection / (this field + 1)
Note: Only used when C3_CLK_SEL is 0, 1, 2, or 3.
2:0C3_CLK_SELRW0x0C3 Clock Selection
0x0 = 819MHz
0x1 = 491MHz
0x2 = 614MHz
0x3 = pll2_div3
0x4 = pll8_div2 (no divided)
0x5 = 1228MHz (no divided)
0x6 = pll2_div2 (no divided)
0x7 = pll8_div1 or pll5_div1 (selected by bit 13, no divided)
PCIE PORTA CLK RESET CONTROL REGISTER​

PCIE_CLK_RES_CTRL_PORTA Offset:0x1F0

BitsFieldTypeResetDescription
31PCIE_DEVICE_TYPE_SELRW0x0PCIe Mode Selection:
1 = EP (Endpoint)
0 = RC (Root Complex)
30PCIE_APP_HOLD_PHY_RSTRW0x1Set this signal to one before the de-assertion of power-on reset sequence to hold the PHY in reset. This can be used to configure your PHY. Synopsys PHYs can be configured through the PHY viewport if desired.
29PCIE_APP_SRIS_MODERW0x0Enable SRIS mode or not for PCIe controller.
28:24PCIE_APP_DEV_NUMRW0x0Device number for RC (Root Complex) mode.
23:16PCIE_APP_BUS_NUMRW0x0Bus number for RC (Root Complex) mode.
15PCIE_APPS_PM_XMT_PMERW0x0Wake Up. If PME is enabled and PME support is configured for current PMCSR D-state, asserting this signal causes the controller to wake from either L1 or L2 state. When the controller has transitioned back to the L0 state, it transmits a PME message and sets the PME_Status. Upon receiving the PME message, the root complex should clear the PME_Status and change the D-state back to D0.
14PCIE_APP_DBI_RO_WR_DISABLERW0x0DBI Read-only Write Disable:
0: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is read-write.
1: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is forced to 0 and is read-only.
13:12RSVDRO0Reserved for future use.
11PCIE_APP_CLK_REQ_NRW0x0-
10PCIE_CLKREQ_INRO0x1Shows the value of Port A CLKREQ# IO input.
9PCIE_SYS_AUX_PWR_DETRW0x1Auxiliary Power Detected. Used to report to the host software that auxiliary power (Vaux) is present.
8PCIE_CLKREQ_OERO0x0-
7PCIE_PERSTN_INRO0x1PERST value from PAD for EP (Endpoint) mode.
6PCIE_LTSSM_ENRW0x0Enable the PCIe controller to start training:
1 = Enable
0 = Hold the LTSSM in detect.quiet
5PCIE_AXI_MSTR_RESETNRW0x0PCIe AXI data master port reset:
0 = Reset
1 = Reset Release
4PCIE_AXI_SLV_RESETNRW0x0PCIe AXI data slave port reset:
0 = Reset
1 = Reset Release
3PCIE_AXI_DBI_RESETNRW0x0PCIe AXI DBI slave port reset:
0 = Reset
1 = Reset Release
2PCIE_AXI_MSTR_CLK_ENRW0x0PCIe AXI data master port clock enable:
0 = Disable
1 = Enable
1PCIE_AXI_SLV_CLK_ENRW0x0PCIe AXI data slave port clock enable:
0 = Disable
1 = Enable
0PCIE_AXI_BUS_CLK_ENRO0PCIe AXI bus clock enable:
0 = Disable
1 = Enable
PCIE PORTA CONTROL LOGIC REGISTER​

PCIE_CTRL_LOGIC_PORTA Offset:0x1F4

BitsFieldTypeResetDescription
31PCIE_IGNORE_PERSTNRW0x0In EP mode, if this bit is set to 1, PCIe controller and PHY will not receive the PERSTN when RC drives it.
30PCIE_FORCE_PERSTNRW0x0In EP mode, SW can set this bit to 1 to force a PERSTN.
29PCIE_CLKREQ_OVRD_VALRW0x0-
28PCIE_CLKREQ_SOURCE_SELRW0x0In EP mode, WAKE# source selection:
1 = The WAKE# pad is driven by pcie_ep_wake_sw bit of PCIe CLK Reset Control Register
0 = The WAKE# pad is driven by PCIe controller
27PCIE_WAKE_OVRD_VALRW0x0-
26PCIE_WAKE_SOURCE_SELRW0x0-
25PCIE_PERSTN_OUTRW0x0-
24PCIE_PERSTN_OERW0x0-
23PCIE_AUXENRW0x1-
22RSVDRO0Reserved for future use
21:20PCIE_RC_WAKEN_DEB_CFGRW0x3PCIe RC WAKEN debounce configuration
19:18PCIE_PERSTN_IN_DEB_CFGRW0x3PCIe PERSTN_IN debounce configuration
17:16PCIE_RXELECIDLE_DEB_CFGRW0x3PCIe RXELECIDLE debounce configuration
15PCIE_WAKEUP_INT_ENRW0x0PCIe wake up enable
14PCIE_WAKEUP_ENRW0x0PCIe wake up event interrupt enable
13:11PCIE_WAKEUP_INT_REGRO0x0PCIe wakeup interrupt status:
Bit 13: PCIe RC WAKEN wakeup event
Bit 12: PCIe EP PERSTN wakeup event
Bit 11: PCIe RXELECIDLE wakeup event
10:7RSVDRO0Reserved for future use
6:4PCIE_WAKEUP_INT_CLRRW0x0SW writes one to these three bits and the corresponding wakeup interrupt status will be cleared:
Bit 6: PCIe RC WAKEN wakeup event
Bit 5: PCIe EP PERSTN wakeup event
Bit 4: PCIe RXELECIDLE wakeup event
3:1PCIE_WAKEUP_MASKRW0x0PCIe wakeup interrupt mask, 1'b1 -> enable:
Bit 3: PCIe RC WAKEN wakeup event
Bit 2: PCIe EP PERSTN wakeup event
Bit 1: PCIe RXELECIDLE wakeup event
0PCIE_SOFT_RESETRW0x0PCIe soft reset:
0 = Release Reset
1 = Reset
PCIE PORTBCDE CLK RESET CONTROL REGISTER​

PCIE_CLK_RES_CTRL_PORTBCDE_X Offset:0x1D0/0x1C8/0x1E0/0x1E8

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30PCIE_APP_HOLD_PHY_RSTRW0x1Set this signal to one before the de-assertion of power-on reset sequence to hold the PHY in reset. This can be used to configure your PHY. Synopsys PHYs can be configured through the PHY viewport if desired.
29PCIE_APP_SRIS_MODERW0x0Enable SRIS mode or not for PCIe controller.
28:24PCIE_APP_DEV_NUMRW0x0Device number for RC (Root Complex) mode.
23:16PCIE_APP_BUS_NUMRW0x0Bus number for RC (Root Complex) mode.
15RSVDRO0Reserved for future use
14PCIE_APP_DBI_RO_WR_DISABLERW0x0DBI Read-only Write Disable:
0: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is read-write.
1: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is forced to 0 and is read-only.
13:12RSVDRO0Reserved for future use
11PCIE_APP_CLK_REQ_NRW0x0-
10PCIE_CLKREQ_INRO0x1Shows the value of Port A CLKREQ# IO input.
9PCIE_SYS_AUX_PWR_DETRW0x1Auxiliary Power Detected. Used to report to the host software that auxiliary power (Vaux) is present.
8PCIE_CLKREQ_OERO0x0-
7PCIE_PERSTN_INRO0x1PERST value from PAD for EP (Endpoint) mode.
6PCIE_LTSSM_ENRW0x0Enable the PCIe controller to start training:
1 = Enable
0 = Hold the LTSSM in detect.quiet
5PCIE_AXI_MSTR_RESETNRW0x0PCIe AXI data master port reset:
0 = Reset
1 = Reset Release
4PCIE_AXI_SLV_RESETNRW0x0PCIe AXI data slave port reset:
0 = Reset
1 = Reset Release
3PCIE_AXI_DBI_RESETNRW0x0PCIe AXI DBI slave port reset:
0 = Reset
1 = Reset Release
2PCIE_AXI_MSTR_CLK_ENRW0x0PCIe AXI data master port clock enable:
0 = Disable
1 = Enable
1PCIE_AXI_SLV_CLK_ENRW0x0PCIe AXI data slave port clock enable:
0 = Disable
1 = Enable
0PCIE_AXI_BUS_CLK_ENRO0PCIe AXI bus clock enable:
0 = Disable
1 = Enable
PCIE PORTBCDE CONTROL LOGIC REGISTER​

PCIE_CTRL_LOGIC_PORTBCDE_X Offset:0x1D4/0x1CC/0x1E4/0x1EC

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30PCIE_APP_HOLD_PHY_RSTRW0x1Set this signal to one before the de-assertion of power-on reset sequence to hold the PHY in reset. This can be used to configure your PHY. Synopsys PHYs can be configured through the PHY viewport if desired.
29PCIE_APP_SRIS_MODERW0x0Enable SRIS mode or not for PCIe controller.
28:24PCIE_APP_DEV_NUMRW0x0Device number for RC (Root Complex) mode.
23:16PCIE_APP_BUS_NUMRW0x0Bus number for RC (Root Complex) mode.
15RSVDRO0Reserved for future use
14PCIE_APP_DBI_RO_WR_DISABLERW0x0DBI Read-only Write Disable:
0: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is read-write.
1: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is forced to 0 and is read-only.
13:12RSVDRO0Reserved for future use
11PCIE_APP_CLK_REQ_NRW0x0-
10PCIE_CLKREQ_INRO0x1Shows the value of Port A CLKREQ# IO input.
9PCIE_SYS_AUX_PWR_DETRW0x1Auxiliary Power Detected. Used to report to the host software that auxiliary power (Vaux) is present.
8PCIE_CLKREQ_OERO0x0-
7PCIE_PERSTN_INRO0x1PERST value from PAD for EP (Endpoint) mode.
6PCIE_LTSSM_ENRW0x0Enable the PCIe controller to start training:
1 = Enable
0 = Hold the LTSSM in detect.quiet
5PCIE_AXI_MSTR_RESETNRW0x0PCIe AXI data master port reset:
0 = Reset
1 = Reset Release
4PCIE_AXI_SLV_RESETNRW0x0PCIe AXI data slave port reset:
0 = Reset
1 = Reset Release
3PCIE_AXI_DBI_RESETNRW0x0PCIe AXI DBI slave port reset:
0 = Reset
1 = Reset Release
2PCIE_AXI_MSTR_CLK_ENRW0x0PCIe AXI data master port clock enable:
0 = Disable
1 = Enable
1PCIE_AXI_SLV_CLK_ENRW0x0PCIe AXI data slave port clock enable:
0 = Disable
1 = Enable
0PCIE_AXI_BUS_CLK_ENRO0PCIe AXI bus clock enable:
0 = Disable
1 = Enable
EMAC0_CLK_RST_CTRL​

EMAC0_CLK_RST_CTRL Offset:0x3E4

BitsFieldTypeResetDescription
31:16RSVDRO0Reserved for future use
15EMAC0_1588_CLK_MUXRW0x0EMAC0 1588 clock select:
0x0 = 24M
0x1 = pll2_125/25/2.5MHz (matches the current speed mode: 1000M/100M/10M)
14EMAC0_CLK_REF_GATERW0x0EMAC0 refclk enable/disable:
0 = TX 25M refclk enable
1 = TX 25M refclk disable
13EMAC0_AXI_MST_IDRW0x01 = EMAC0 AXI MST interface uses single ID to issue transfer
0 = EMAC0 AXI MST interface uses multi ID to issue transfer
12EMAC0_PHY_INTR_ENRW0x01 = EMAC0 PHY PMT interrupt mask enable
0 = EMAC0 PHY PMT interrupt mask disable
11:10RSVDRO0Reserved for future use
9EMAC0_LPI_INTR_ENRW0x01 = EMAC0 LPI interrupt mask enable
0 = EMAC0 LPI interrupt mask disable
8EMAC0_RGMII_TXC_SRC_SELRW0x0This bit is only valid in RGMII mode. EMAC RGMII TX clock source selection:
0 = TX clock source from RX clock
1 = TX clock source from SoC
7EMAC_RX_REFCLK_PHASE_SELRW0x0EMAC0 RX REFCLK phase select:
1 = Refclk inverted
0 = Refclk normal
6EMAC_RMII_TX_REFCLK_PHASE_SELRW0x0EMAC0 RMII TX REFCLK phase select:
1 = RMII refclk inverted
0 = RMII refclk normal
5RSVDRO0Reserved for future use
4:3EMAC0_PHY_SELECTRW0x0EMAC0 PHY SELECT:
2'b10 = MII/GMII
2'b01 = RGMII
2'b00 = RMII
2RSVDRO0Reserved for future use
1EMAC0_BUS_RSTRW0x0EMAC0 AXI Bus Reset:
0 = Reset
1 = Reset Release
0EMAC0_BUS_ENRW0x0EMAC0 AXI Bus Clock Enable:
0 = Disable
1 = Enable
EMAC1_CLK_RST_CTRL​

EMAC1_CLK_RST_CTRL Offset:0x3EC

BitsFieldTypeResetDescription
31:16RSVDRO0Reserved for future use
15EMAC1_1588_CLK_MUXRW0x0EMAC1 1588 clock select:
0x0 = 24M
0x1 = pll2_125/25/2.5MHz (matches the current speed mode: 1000M/100M/10M)
14EMAC1_CLK_REF_GATERW0x0EMAC1 refclk enable/disable:
0 = TX 25M refclk enable
1 = TX 25M refclk disable
13EMAC1_AXI_MST_IDRW0x01 = EMAC1 AXI MST interface uses single ID to issue transfer
0 = EMAC1 AXI MST interface uses multi ID to issue transfer
12EMAC1_PHY_INTR_ENRW0x01 = EMAC1 PHY PMT interrupt mask enable
0 = EMAC1 PHY PMT interrupt mask disable
11:10RSVDRO0Reserved for future use
9EMAC1_LPI_INTR_ENRW0x01 = EMAC1 LPI interrupt mask enable
0 = EMAC1 LPI interrupt mask disable
8EMAC1_RGMII_TXC_SRC_SELRW0x0This bit is only valid in RGMII mode. EMAC1 RGMII TX clock source selection:
0 = TX clock source from RX clock
1 = TX clock source from SoC
7EMAC_RX_REFCLK_PHASE_SELRW0x0EMAC1 RX REFCLK phase select:
1 = Refclk inverted
0 = Refclk normal
6EMAC_RMII_TX_REFCLK_PHASE_SELRW0x0EMAC1 RMII TX REFCLK phase select:
1 = RMII refclk inverted
0 = RMII refclk normal
5RSVDRO0Reserved for future use
4:3EMAC1_PHY_SELECTRW0x0EMAC1 PHY SELECT:
2'b10 = MII/GMII
2'b01 = RGMII
2'b00 = RMII
2RSVDRO0Reserved for future use
1EMAC1_BUS_RSTRW0x0EMAC1 AXI Bus Reset:
0 = Reset
1 = Reset Release
0EMAC1_BUS_ENRW0x0EMAC1 AXI Bus Clock Enable:
0 = Disable
1 = Enable
EMAC2_CLK_RST_CTRL​

EMAC2_CLK_RST_CTRL Offset:0x248

BitsFieldTypeResetDescription
31:16RSVDRO0Reserved for future use
15EMAC2_1588_CLK_MUXRW0x0EMAC2 1588 clock select:
0x0 = 24M
0x1 = pll2_125/25/2.5MHz (matches the current speed mode: 1000M/100M/10M)
14EMAC2_CLK_REF_GATERW0x0EMAC2 refclk enable/disable:
0 = TX 25M refclk enable
1 = TX 25M refclk disable
13EMAC2_AXI_MST_IDRW0x01 = EMAC2 AXI MST interface uses single ID to issue transfer
0 = EMAC2 AXI MST interface uses multi ID to issue transfer
12EMAC2_PHY_INTR_ENRW0x01 = EMAC2 PHY interrupt enable
0 = EMAC2 PHY interrupt disable
11:10RSVDRO0Reserved for future use
9EMAC2_LPI_INTR_ENRW0x01 = EMAC2 LPI interrupt mask enable
0 = EMAC2 LPI interrupt mask disable
8EMAC2_RGMII_TXC_SRC_SELRW0x0This bit is only valid in RGMII mode. EMAC2 RGMII TX clock source selection:
0 = TX clock source from RX clock
1 = TX clock source from SoC
7EMAC_RMII_RX_REFCLK_PHASE_SELRW0x0EMAC2 RMII RX REFCLK phase select:
1 = RMII refclk inverted
0 = RMII refclk normal
6EMAC_RMII_TX_REFCLK_PHASE_SELRW0x0EMAC2 RMII TX REFCLK phase select:
1 = RMII refclk inverted
0 = RMII refclk normal
5RSVDRO0Reserved for future use
4:3EMAC2_PHY_SELECTRW0x0EMAC2 PHY SELECT:
2'b01 = MII/GMII/RGMII
2'b10 = RMII
2EMAC2_RMII_REFCLK_OERW0x0EMAC2 RMII Clock Direction:
1 = Output (Clock provided by SoC)
0 = Input (Clock provided by external PHY)
1EMAC2_BUS_RSTRW0x0EMAC2 AXI Bus Reset:
0 = Reset
1 = Reset Release
0EMAC2_BUS_ENRW0x0EMAC2 AXI Bus Clock Enable:
0 = Disable
1 = Enable
ESPI_CLK_RST_CTRL​

ESPI_CLK_RST_CTRL Offset:0x240

BitsFieldTypeResetDescription
31:8RSVDRO0Reserved for future use
7ESPI_SCLK_OVERRIDERW0x0ESPI SCLK Override:
0 = ESPI SCLK selected by ESPI module internal register
1 = ESPI SCLK selected by ESPI_SCLK_SELECT bits
6:4ESPI_SCLK_SELECTRW0x0ESPI SCLK Select (valid when ESPI_SCLK_OVERRIDE = 1):
0x0 = 20MHz (from pll2)
0x1 = 25MHz (from pll2)
0x2 = 33MHz (from pll2)
0x3 = 50MHz (from pll2)
0x4 = 66MHz (from pll2)
3ESPI_SCLK_ENRW0x0ESPI SCLK Clock Enable:
0 = Disable
1 = Enable
2ESPI_SCLK_RSTRW0x0ESPI SCLK Reset:
0 = Reset
1 = Reset Release
1ESPI_MCLK_ENRW0x0ESPI MCLK Clock Enable:
0 = Disable
1 = Enable
0ESPI_MCLK_RSTRW0x0ESPI MCLK Reset:
0 = Reset
1 = Reset Release
ISIM VCLK CTRL​

SNR_ISIM_VCLK_CTRL Offset:0x3F8

BitsFieldTypeResetDescription
31RSVDRO0Reserved for future use
30:27ISIM_VCLK_OUT_DIV3RW0xBDivider for ISIM VCLK OUT3:
ISIM_VCLK_OUT3 = CAM_MCLK3 / (this field + 1)
26:25CAM_MCLK3_SELRW0x0CAM MCLK3 Source Select:
0x0 = 27MHz (pll1_409M/15)
0x1 = 24MHz (pll2_div5/25)
0x2 = 25MHz (pll2_div6/20)
0x3 = 26MHz (pll1_409M/16)
24CAM_MCLK3_ENRW0x0CAM MCLK3 Enable:
0 = Disable
1 = Enable
23RSVDRO0Reserved for future use
22:19ISIM_VCLK_OUT_DIV2RW0xBDivider for ISIM VCLK OUT2:
ISIM_VCLK_OUT2 = CAM_MCLK2 / (this field + 1)
18:17CAM_MCLK2_SELRW0x0CAM MCLK2 Source Select:
0x0 = 27MHz (pll1_409M/15)
0x1 = 24MHz (pll2_div5/25)
0x2 = 25MHz (pll2_div6/20)
0x3 = 26MHz (pll1_409M/16)
16CAM_MCLK2_ENRW0x0CAM MCLK2 Enable:
0 = Disable
1 = Enable
15RSVDRO0Reserved for future use
14:11ISIM_VCLK_OUT_DIV1RW0xBDivider for ISIM VCLK OUT1:
ISIM_VCLK_OUT1 = CAM_MCLK1 / (this field + 1)
10:9CAM_MCLK1_SELRW0x0CAM MCLK1 Source Select:
0x0 = 27MHz (pll1_409M/15)
0x1 = 24MHz (pll2_div5/25)
0x2 = 25MHz (pll2_div6/20)
0x3 = 26MHz (pll1_409M/16)
8CAM_MCLK1_ENRW0x0CAM MCLK1 Enable:
0 = Disable
1 = Enable
7RSVDRO0Reserved for future use
6:3ISIM_VCLK_OUT_DIV0RW0xBDivider for ISIM VCLK OUT0:
ISIM_VCLK_OUT0 = CAM_MCLK0 / (this field + 1)
2:1CAM_MCLK0_SELRW0x0CAM MCLK0 Source Select:
0x0 = 27MHz (pll1_409M/15)
0x1 = 24MHz (pll2_div5/25)
0x2 = 25MHz (pll2_div6/20)
0x3 = 26MHz (pll1_409M/16)
0CAM_MCLK0_ENRW0x0CAM MCLK0 Enable:
0 = Disable
1 = Enable

CIUDRAGON​

DRAGON DMA SUBSYS SDMA0 RESET SIGNAL​

DMASYS_S0_RSTN Reset when DRAGON DMA SUBSYS SDMA0 RESET SIGNAL = 0 Offset:0x204

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS SDMA1 RESET SIGNAL​

DMASYS_S1_RSTN Reset when DRAGON DMA SUBSYS SDMA1 RESET SIGNAL = 0 Offset:0x208

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS ADMA0 RESET SIGNAL​

DMASYS_A0_RSTN Reset when DRAGON DMA SUBSYS ADMA0 RESET SIGNAL = 0 Offset:0x20C

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS ADMA1 RESET SIGNAL​

DMASYS_A1_RSTN Reset when DRAGON DMA SUBSYS ADMA1 RESET SIGNAL = 0 Offset:0x210

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS ADMA2 RESET SIGNAL​

DMASYS_A2_RSTN Reset when DRAGON DMA SUBSYS ADMA2 RESET SIGNAL = 0 Offset:0x214

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS ADMA3 RESET SIGNAL​

DMASYS_A3_RSTN Reset when DRAGON DMA SUBSYS ADMA3 RESET SIGNAL = 0 Offset:0x218

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS ADMA4 RESET SIGNAL​

DMASYS_A4_RSTN Reset when DRAGON DMA SUBSYS ADMA4 RESET SIGNAL = 0 Offset:0x21C

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS ADMA5 RESET SIGNAL​

DMASYS_A5_RSTN Reset when DRAGON DMA SUBSYS ADMA5 RESET SIGNAL = 0 Offset:0x220

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS ADMA6 RESET SIGNAL​

DMASYS_A6_RSTN Reset when DRAGON DMA SUBSYS ADMA6 RESET SIGNAL = 0 Offset:0x224

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS ADMA7 RESET SIGNAL​

DMASYS_A7_RSTN Reset when DRAGON DMA SUBSYS ADMA7 RESET SIGNAL = 0 Offset:0x228

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS RESET SIGNAL​

DMASYS_RSTN Reset when DRAGON DMA SUBSYS RESET SIGNAL = 0 Offset:0x22C

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS SDMA RESET SIGNAL​

DMASYS_SDMA_RSTN Reset when DRAGON DMA SUBSYS SDMA RESET SIGNAL = 0 Offset:0x230

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS CLK ENABLE​

DMASYS_CLK_EN Clock is enabled when DRAGON DMA SUBSYS CLK ENABLE = 1 Offset:0x234

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
DRAGON DMA SUBSYS SDMA CLK ENABLE​

DMASYS_SDMA_CLK_EN Clock is enabled when DRAGON DMA SUBSYS SDMA CLK ENABLE = 1 Offset:0x238

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
C2_TCM_PIPE_CLK_EN​

C2_TCM_PIPE_CLK_EN Clock is enabled when the en-clock control bit for the C2 TCM bus access path is 1 Offset:0x244

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset
C3_TCM_PIPE_CLK_EN​

C3_TCM_PIPE_CLK_EN Clock is enabled when the en-clock control bit for the C3 TCM bus access path is 1 Offset:0x248

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RESET_ENRW0x0Reset Control:
0 = Reset
1 = Release Reset

APB2CLOCK​

CLOCK/RESET CONTROL REGISTER FOR UART 1​

APBC_SEC_UART1_CLK_RST Offset:0x0

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 57.6 MHz
0x1 = 14.74 MHz
0x2 = 48 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1UART Reset Generation (resets both APB and Functional domains):
0 = Release Reset
1 = Reset
1FNCLKRW0x0UART Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0UART APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR SSP 2​

APBC_SEC_SSP2_CLK_RST Offset:0x4

BitsFieldTypeResetDescription
31:8RSVDRO0Reserved for future use
7SEL_SSP_FUNC_CLKRW0x0AC97 Clock Switch:
This bit enables the SSP module to switch clocks internally.
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 6.4 MHz
0x1 = 12.8 MHz
0x2 = 25.6 MHz
0x3 = 51.2 MHz
0x4 = 3.2 MHz
0x5 = 1.6 MHz
0x6 = 800 kHz
0x7 = 1 MHz or i2s_bitclk (MN divided from 307.2 MHz)
3SEL_1MHZRW0x0SSPA 1MHz clock or i2s_bitclk (MN divided from PLL_div8 307.2 MHz):
0x0 = 1 MHz
0x1 = i2s_bitclk
2RSTRW0x1SSP 2 Reset Generation (resets both APB and functional domains):
0 = Release Reset
1 = Reset
1FNCLKRW0x0SSP 2 Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0SSP 2 APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR TWSI3​

APBC_SEC_TWSI3_CLK_RST Offset:0x8

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 31.5 MHz
0x1 = 51.2 MHz
0x2 = 61.44 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1TWSI Reset Generation (resets both APB and functional domains):
0 = Release Reset
1 = Reset
1FNCLKRW0x0TWSI0 Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0TWSI0 APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR RTC​

APBC_SEC_RTC_CLK_RST Offset:0xC

BitsFieldTypeResetDescription
31:8RSVDRO0Reserved for future use
7PM_POWER_SENSORRW0x0Power enabled:
This field enables register read/write access for the RTC module by indicating power enable. Set this field to 0x1 before enabling RTC operations.
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 32 kHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x0RTC Reset Generation (resets both APB and functional domain):
0 = Release Reset
1 = Reset
1FNCLKRW0x1RTC Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0RTC APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR SEC TIMERS​

APBC_SEC_TIMERS_CLK_RST Offset:0x10

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 12.8 MHz
0x1 = 32 kHz
0x2 = 6.4 MHz
0x3 = 3.00 MHz
0x4 = 1 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1Timers Reset Generation (resets both APB and functional domains):
0 = Release Reset
1 = Reset
1FNCLKRW0x0Timers Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0Timers APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR JTAG_SW​

APBC_SEC_JTAG_SW_CLK_RST Offset:0x18

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
JTAG_SW does not have a functional clock
3RSVDRO0Reserved for future use
2RSTRW0x1Reset Generation (resets both APB and functional domains):
0 = Release Reset
1 = Reset
1FNCLKRW0x0Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
CLOCK/RESET CONTROL REGISTER FOR SEC_GPIO​

APBC_SEC_GPIO_CLK_RST Offset:0x1C

BitsFieldTypeResetDescription
31:7RSVDRO0Reserved for future use
6:4FNCLKSELRW0x0Functional Clock Select:
GPIO does not have a functional clock
3RSVDRO0Reserved for future use
2RSTRW0x1Reset Generation (resets both APB and functional domains):
0 = Release Reset
1 = Reset
1FNCLKRW0x0Functional Clock Enable/Disable:
0x0 = Disable
0x1 = Enable
0APBCLKRW0x0APB Bus Clock Enable/Disable:
0x0 = Disable
0x1 = Enable

RCPU_SYSCTRL​

CLOCK/RESET CONTROL REGISTER FOR R_ESPI​

R_ESPI_CLK_RES_CTRL Offset:0xDC

BitsFieldTypeResetDescription
31:9RSVDRO0Reserved for future use
8R_ESPI_SCLK_OVERRIDERW0x0R_ESPI SCLK Override:
0 = R_ESPI SCLK selected by R_ESPI module internal register
1 = R_ESPI SCLK selected by R_ESPI_SCLK_SELECT field
7RSVDRO0Reserved for future use
6:4R_ESPI_SCLK_SELECTRW0x0R_ESPI SCLK Select (used when R_ESPI_SCLK_OVERRIDE is 1):
0x0 = 20 MHz (from pll2)
0x1 = 25 MHz (from pll2)
0x2 = 33 MHz (from pll2)
0x3 = 50 MHz (from pll2)
0x4 = 66 MHz (from pll2)
3:2RSVDRO0Reserved for future use
1R_ESPI_SCLK_ENRW0x0R_ESPI SCLK Clock Enable:
0 = Disable
1 = Enable
0R_ESPI_SCLK_RSTRW0x0R_ESPI SCLK Reset:
0 = Reset
1 = Release Reset
CLOCK/RESET CONTROL REGISTER FOR R_CAN​

R_CANn_CLK_RES_CTRL(n = 0~4) Offset:0x4C/0xF0/0xF4/0xF8/0xFC

BitsFieldTypeResetDescription
31:6RSVDRO0Reserved for future use
5:4R_CAN_FCLK_SELRW0x0R_CAN Functional Clock Select:
0x0 = 20 MHz (from pll6)
0x1 = 40 MHz (from pll6)
0x2 = 80 MHz (from pll6)
0x3 = Reserved
3RSVDRO0Reserved for future use
2R_CAN_PCLK_ENRW0x0Enable bit for R_CAN PCLK:
0x0 = Disable
0x1 = Enable
1R_CAN_FCLK_ENRW0x0Enable bit for R_CAN FCLK:
0x0 = Disable
0x1 = Enable
0SW_RSTNRW0x0Reset Control:
0 = Reset
1 = Release Reset
CLOCK/RESET CONTROL REGISTER FOR CODEC_SYS​

R_IRCn_CLK_RES_CTRL(n = 0/1) Offset:0x48/0xEC

BitsFieldTypeResetDescription
31:3RSVDRO0Reserved for future use
2R_IRC_PCLK_ENRW0x0Enable bit for R_IRC PCLK:
0x0 = Disable
0x1 = Enable
1RSVDRO0Reserved for future use
0SW_RSTNRW0x0Reset Control:
0 = Reset
1 = Release Reset
CLOCK/RESET CONTROL REGISTER FOR R_SSPA​

R_SSPAn_SYSCLK_RES_CTRL(n = 0/1) Offset:0x70/0x44

BitsFieldTypeResetDescription
31:19RSVDRO0Reserved for future use
18:8SYSCLK_FCLK_DIVRW0x0SYSCLK Functional Clock Divider:
Formula:
fclk = source_clk / (SYSCLK_FCLK_DIV + 1)
7:6RSVDRO0Reserved for future use
5:4SYSCLK_FCLK_SELRW0x0SYSCLK Functional Clock Select:
0x0 = 24.576 MHz
0x1 = 245.76 MHz
0x2 = 25.6 MHz
0x3 = 3.2 MHz
3RSVDRO0Reserved for future use
2SYSCLK_PCLK_ENRW0x0Enable bit for SYSCLK PCLK:
0x0 = Disable
0x1 = Enable
1SYSCLK_FCLK_ENRW0x0Enable bit for SYSCLK FCLK:
0x0 = Disable
0x1 = Enable
0SYSCLK_SW_RSTNRW0x0Reset Control:
0 = Reset
1 = Release Reset
CLOCK/RESET CONTROL REGISTER FOR RESAMPLE​

RSMP_CLK_CRL Offset:0xBC

BitsFieldTypeResetDescription
31:2RSVDRO0Reserved for future use
1RSMP_CLK_ENRW0x0Enable bit for Resample Clock:
0x0 = Disable
0x1 = Enable
0RSMP_RST_ENRW0x0Enable bit for Resample Reset:
0x0 = Disable
0x1 = Enable
EMAC3_CLK_RST_CTRL​

R_GMAC_CLK_RES_CTRL Offset:0xE4

BitsFieldTypeResetDescription
31:16RSVDRO0Reserved for future use
15EMAC3_1588_CLK_MUXRW0x0EMAC 1588 Clock Select:
0x0 = 24 MHz
0x1 = pll2_125/25/2.5 MHz (matches current speed mode: 1000M/100M/10M)
14EMAC3_CLK_REF_GATERW0x0EMAC refclk enable/disable:
0 = Enable
1 = Disable
13EMAC3_AXI_MST_IDRW0x0EMAC3 AXI Master ID Mode:
1 = Use single ID to issue transfer
0 = Use multi ID to issue transfer
12EMAC3_PHY_INTR_ENRW0x0EMAC3 PHY PMT Interrupt Mask:
1 = Enable Mask
0 = Disable Mask
11:10RSVDRO0Reserved for future use
9EMAC3_LPI_INTR_ENRW0x0EMAC3 LPI Interrupt Mask:
1 = Enable Mask
0 = Disable Mask
8EMAC3_RGMII_TXC_SRC_SELRW0x0EMAC RGMII TX Clock Source Selection (Valid only in RGMII mode):
0 = TX clock source from RX clock
1 = TX clock source from SoC
7EMAC_RX_REFCLK_PHASE_SELRW0x0EMAC3 RX REFCLK phase select:
1 = Invert refclk
0 = Normal refclk
6EMAC_RMII_TX_REFCLK_PHASE_SELRW0x0EMAC3 RMII TX REFCLK phase select:
1 = Invert RMII refclk
0 = Normal RMII refclk
5RSVDRO0Reserved for future use
4:3EMAC3_PHY_SELECTRW0x0EMAC3 PHY Interface Select:
2'b10 = MII/GMII
2'b01 = RGMII
2'b00 = RMII
2RSVDRO0Reserved for future use
1EMAC3_BUS_RSTRW0x0EMAC3 AXI Bus Reset:
0 = Reset
1 = Release Reset
0EMAC3_BUS_ENRW0x0EMAC3 AXI Bus Clock Enable:
0 = Disable
1 = Enable

RCPU_UARTCTRL​

CLOCK/RESET CONTROL REGISTER FOR RCPU UART​

R_UARTn_CLK_RST(n = 0~5) Offset:0x00/0x04/0x08/0x0C/0x10/0x14

BitsFieldTypeResetDescription
31:19RSVDRO0Reserved for future use
18:8FNCLKDIVRW0x0Functional Clock Divider:
Real Divider = (FNCLKDIV + 1)
7:6RSVDRO0Reserved for future use
5:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 14 MHz
0x1 = 245.76 MHz
0x2 = 25.6 MHz
0x3 = 58 MHz
3RSVDRO0Reserved for future use
2RSTRW0x1Reset Generation (resets both APB and functional domains):
0 = Release Reset
1 = Reset
1FNCLKRW0x0Functional Clock Enable/Disable:
0 = Disable
1 = Enable
0APBCLKRW0x0APB Bus Clock Enable/Disable:
0 = Disable
1 = Enable

RCPU_I2SCTRL​

RCPU I2S0 TX RX CLOCK CONTROL REGISTER​

RCPU_I2S0_TX_RX_CLK_CTRL Offset:0x60

BitsFieldTypeResetDescription
31:18RSVDRO0Reserved for future use
17:16FCLK_SRC_SELRW0x0Functional Clock Source:
0x0 = 24.576 MHz
0x1 = 245.76 MHz
All other values = Reserved
15RSVDRO0Reserved for future use
14:4FCLK_DIVRW0x9fFunctional Clock Divider:
Formula:
fclk = FCLK_SRC / (FCLK_DIV + 1)
3RSVDRO0Reserved for future use
2FCLK_ENRW0x0Functional Clock Enable:
0 = Disable
1 = Enable
1BUS_CLK_ENRW0x0Bus Clock Enable:
0 = Disable
1 = Enable
0SW_RSTNRW0x0Reset Control for I2S and ADMA:
0 = Reset
1 = Release Reset
RCPU I2S1 TX RX CLOCK CONTROL REGISTER​

RCPU_I2S1_TX_RX_CLK_CTRL Offset:0x64

BitsFieldTypeResetDescription
31:18RSVDRO0Reserved for future use
17:16FCLK_SRC_SELRW0x0Functional Clock Source:
0x0 = 24.576 MHz
0x1 = 245.76 MHz
All other values = Reserved
15RSVDRO0Reserved for future use
14:4FCLK_DIVRW0x9fFunctional Clock Divider:
Formula:
fclk = FCLK_SRC / (FCLK_DIV + 1)
3RSVDRO0Reserved for future use
2FCLK_ENRW0x0Functional Clock Enable:
0 = Disable
1 = Enable
1BUS_CLK_ENRW0x0Bus Clock Enable:
0 = Disable
1 = Enable
0SW_RSTNRW0x0Reset Control for I2S and ADMA:
0 = Reset
1 = Release Reset
RCPU I2S2 EDP TX RX CLOCK CONTROL REGISTER​

RCPU_EDP_I2S2_TX_RX_CLK_CTRL This register controls audio SSPA and ADMA clocks. ADMA and SSPA use the same bus clock, and SSPA has a separate functional clock. Offset:0x68

BitsFieldTypeResetDescription
31:18RSVDRO0Reserved for future use
17:16FCLK_SRC_SELRW0x0SSPA functional clock source:
0x0 = i2s2_sysclk
All other values = Reserved
15RSVDRO0Reserved for future use
14:4FCLK_DIVRW0x9fFunctional Clock Divider:
Formula:
fclk = FCLK_SRC / (FCLK_DIV + 1)
3RSVDRO0Reserved for future use
2FCLK_ENRW0x0Functional Clock Enable:
0 = Disable
1 = Enable
1BUS_CLK_ENRW0x0Bus Clock Enable:
0 = Disable
1 = Enable
0SW_RSTNRW0x0Reset Control for I2S and ADMA:
0 = Reset
1 = Release Reset
RCPU I2S3 EDP TX RX CLOCK CONTROL REGISTER​

RCPU_EDP_I2S3_TX_RX_CLK_CTRL This register controls audio SSPA and ADMA clocks. ADMA and SSPA use the same bus clock, and SSPA has a separate functional clock. Offset:0x6C

BitsFieldTypeResetDescription
31:18RSVDRO0Reserved for future use
17:16FCLK_SRC_SELRW0x0SSPA functional clock source:
0x0 = i2s3_sysclk
All other values = Reserved
15RSVDRO0Reserved for future use
14:4FCLK_DIVRW0x9fFunctional Clock Divider:
Formula:
fclk = FCLK_SRC / (FCLK_DIV + 1)
3RSVDRO0Reserved for future use
2FCLK_ENRW0x0Functional Clock Enable:
0 = Disable
1 = Enable
1BUS_CLK_ENRW0x0Bus Clock Enable:
0 = Disable
1 = Enable
0SW_RSTNRW0x0Reset Control for I2S and ADMA:
0 = Reset
1 = Release Reset
CLOCK/RESET CONTROL REGISTER FOR EDP_MCLK​

RCPU_EDP_I2S2_SYSCLK_RES_CTRL Offset:0x44

BitsFieldTypeResetDescription
31:18RSVDRO0Reserved for future use
17:16SYSCLK_SELRW0x0Sysclk Source Select:
0x0 = 24.576 MHz
0x1 = 245.76 MHz
All other values = Reserved
15RSVDRO0Reserved for future use
14:4SYSCLK_DIVRW0x1ffSysclk Divider:
Formula:
sysclk = SYSCLK_SRC / (SYSCLK_DIV + 1)
3RSVDRO0Reserved for future use
2SYSCLK_ENRW0x0Sysclk Enable:
0 = Disable
1 = Enable
1BUS_ENRW0x0Bus Clock Enable:
0 = Disable
1 = Enable
0SW_RSTNRW0x0Sysclk Software Reset:
0 = Reset
1 = Release Reset
CLOCK/RESET CONTROL REGISTER FOR EDP1_MCLK​

RCPU_EDP1_I2S3_SYSCLK_RES_CTRL Offset:0x54

BitsFieldTypeResetDescription
31:18RSVDRO0Reserved for future use
17:16SYSCLK_SELRW0x0Sysclk Source Select:
0x0 = 24.576 MHz
0x1 = 245.76 MHz
All other values = Reserved
15RSVDRO0Reserved for future use
14:4SYSCLK_DIVRW0x1ffSysclk Divider:
Formula:
sysclk = SYSCLK_SRC / (SYSCLK_DIV + 1)
3RSVDRO0Reserved for future use
2SYSCLK_ENRW0x0Sysclk Enable:
0 = Disable
1 = Enable
1BUS_ENRW0x0Bus Clock Enable:
0 = Disable
1 = Enable
0SW_RSTNRW0x0Sysclk Software Reset:
0 = Reset
1 = Release Reset

RCPU_SPICTRL​

CLOCK/RESET CONTROL REGISTER FOR RCPU SSP​

R_SSPn_CLK_RST (n = 0~1) Offset:0x0/0x4

BitsFieldTypeResetDescription
31:19RSVDRO0Reserved for future use
18:8FNCLKDIVRW0x0Functional Clock Divider:
Real Divider = (FNCLKDIV + 1)
7:6RSVDRO0Reserved for future use
5:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 24.576 MHz
0x1 = 245.76 MHz
0x2 = 25.6 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1Reset Generation:
Resets both APB and functional domains.
0 = Release Reset
1 = Reset
1FNCLKRW0x0Functional Clock Enable/Disable:
0 = Disable
1 = Enable
0APBCLKRW0x0APB Bus Clock Enable/Disable:
0 = Disable
1 = Enable
CLOCK/RESET CONTROL REGISTER FOR RCPU PWR SSP​

PWR_SSP_CLK_RST Offset:0x8

BitsFieldTypeResetDescription
31:19RSVDRO0Reserved for future use
18:8FNCLKDIVRW0x0Functional Clock Divider:
Real Divider = (FNCLKDIV + 1)
7:6RSVDRO0Reserved for future use
5:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 24.576 MHz
0x1 = 245.76 MHz
0x2 = 25.6 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1Reset Generation:
Resets both APB and functional domains.
0 = Release Reset
1 = Reset
1FNCLKRW0x0Functional Clock Enable/Disable:
0 = Disable
1 = Enable
0APBCLKRW0x0APB Bus Clock Enable/Disable:
0 = Disable
1 = Enable

RCPU_I2CCTRL​

CLOCK/RESET CONTROL REGISTER FOR RCPU I2C​

R_I2Cn_CLK_RST (n = 0~1) Offset:0x0/0x4

BitsFieldTypeResetDescription
31:19RSVDRO0Reserved for future use
18:8FNCLKDIVRW0x0Functional Clock Divider:
Real Divider = (FNCLKDIV + 1)
7:6RSVDRO0Reserved for future use
5:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 24.576 MHz
0x1 = 245.76 MHz
0x2 = 25.6 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1Reset Generation:
Resets both APB and functional domains.
0 = Release Reset
1 = Reset
1FNCLKRW0x0Functional Clock Enable/Disable:
0 = Disable
1 = Enable
0APBCLKRW0x0APB Bus Clock Enable/Disable:
0 = Disable
1 = Enable
CLOCK/RESET CONTROL REGISTER FOR RCPU PWR I2C​

PWR_I2C_CLK_RST Offset:0x8

BitsFieldTypeResetDescription
31:19RSVDRO0Reserved for future use
18:8FNCLKDIVRW0x0Functional Clock Divider:
Real Divider = (FNCLKDIV + 1)
7:6RSVDRO0Reserved for future use
5:4FNCLKSELRW0x0Functional Clock Select:
0x0 = 24.576 MHz
0x1 = 245.76 MHz
0x2 = 25.6 MHz
All other values = Reserved, do not use
3RSVDRO0Reserved for future use
2RSTRW0x1Reset Generation:
Resets both APB and Functional domains.
0 = Release Reset
1 = Reset
1FNCLKRW0x0Functional Clock Enable/Disable:
0 = Disable
1 = Enable
0APBCLKRW0x0APB Bus Clock Enable/Disable:
0 = Disable
1 = Enable

RCPU_PMU​

AON_PER_CLK_RST_CTRL​

AON_PER_CLK_RST_CTRL Offset:0x2C

BitsFieldTypeResetDescription
31:6RSVDRO0Reserved for future use
5IPC_MSA_CLK_ENRW0x0IPC to MSA Clock Enable/Disable:
0 = Disable
1 = Enable
4IPC_MSA_RSTNRW0x0IPC MSA Reset:
0 = Reset
1 = Release Reset
3IPC_CP_CLK_ENRW0x0IPC to CP Clock Enable/Disable:
0 = Disable
1 = Enable
2IPC_CP_RSTNRW0x0IPC CP Reset:
0 = Reset
1 = Release Reset
1IPC_AP_CLK_ENRW0x0IPC to AP Clock Enable/Disable:
0 = Disable
1 = Enable
0IPC_AP_RSTNRW0x0IPC AP Reset:
0 = Reset
1 = Release Reset
MCU_TIMER_CLK_RST_CTRL​

MCU_TIMERn_CLK_RST_CTRL (n = 1~4) Offset:0x4C/0x70/0x78/0x7C

BitsFieldTypeResetDescription
31:19RSVDRO0Reserved for future use
18:8TIMER_FCLK_DIVRW0x0Timer Functional Clock Divider:
Timer FCLK = Source Clock / (TIMER_FCLK_DIV + 1)
7:6RSVDRO0Reserved for future use
5:4TIMER_FCLK_SELRW0x0Timer Functional Clock Select:
0x0 = 25.6 MHz
0x1 = 12.8 MHz
0x2 = 3.2 MHz
0x3 = Reserved
3RSVDRO0Reserved for future use
2TIMER_PCLK_ENRW0x0Timer PCLK Enable/Disable:
0 = Disable
1 = Enable
1TIMER_FCLK_ENRW0x0Timer FCLK Enable/Disable:
0 = Disable
1 = Enable
0TIMER_SW_RSTNRW0x0Timer Software Reset:
0 = Reset
1 = Release Reset
FORCE_CHIP_RST​

FORCE_CHIP_RST Offset:0x58

BitsFieldTypeResetDescription
31:16RSVDRO0Reserved for future use
15:0FORCE_CHIP_RSTRW0x1Force Chip Reset (force_chip_rstn):
0 = Reset
1 = Release Reset
GPIO_AND_EDGE_CLK_RST_CTRL​

GPIO_AND_EDGE_CLK_RST_CTRL Offset:0x74

BitsFieldTypeResetDescription
31:5RSVDRO0Reserved for future use
4GPIO_LP_CK_ENRW0x0GPIO Low Power Clock Enable/Disable:
0 = Disable
1 = Enable
3EDGE_DET_PCLK_ENRW0x0Edge Detector PCLK Enable/Disable:
0 = Disable
1 = Enable
2EDGE_DET_RSTNRW0x0Edge Detector Software Reset:
0 = Reset
1 = Release Reset
1GPIO_PCLK_ENRW0x0GPIO PCLK Enable/Disable:
0 = Disable
1 = Enable
0GPIO_RSTNRW0x0GPIO Software Reset:
0 = Reset
1 = Release Reset
RCPU_BUS_CLK_CTRL​

RCPU_BUS_CLK_CTRL Offset:0xC0

BitsFieldTypeResetDescription
31:9RSVDRO0Reserved for future use
8BUS_CLK_FC_REQRW0x0Bus Frequency Change Request:
Write 1 to trigger bus frequency change.
This bit will be automatically cleared when the frequency change is done.
7:6RSVDRO0Reserved for future use
5:3AXI_CLK_DIVRW0x0AXI Clock Divider:
rcpu_sys_axi_clk = rcpu_sys_clk / (AXI_CLK_DIV + 1)
2:0APB_CLK_DIVRW0x1APB Clock Divider:
rcpu_sys_apb_clk = rcpu_sys_axi_clk / (APB_CLK_DIV + 1)
Note: APB_CLK_DIV must be > 1 (resulting divider ≥ 2). Writing 0 to this field is invalid.
RT24_CORE0_CLK_CTRL​

RT24_CORE0_CLK_CTRL Offset:0xC4

BitsFieldTypeResetDescription
31:9RSVDRO0Reserved for future use
8CORE_CLK_FC_REQRW0x0Core Frequency Change Request:
Write 1 to trigger core frequency change.
This bit will be automatically cleared when the frequency change is done.
7:6RSVDRO0Reserved for future use
5:4CORE_CLK_SELRW0x0Core0 Clock Source Select:
0x0 = rcpu_sys_clk
0x1 = 614 MHz
0x2 = 491 MHz
0x3 = Reserved
3:2RSVDRO0Reserved for future use
1:0CORE_CLK_DIVRW0x0Core Clock Divider = this field + 1
RT24_CORE1_CLK_CTRL​

RT24_CORE1_CLK_CTRL Offset:0xC8

BitsFieldTypeResetDescription
31:9RSVDRO0Reserved for future use
8CORE_CLK_FC_REQRW0x0Core Frequency Change Request:
Write 1 to trigger core frequency change.
This bit will be automatically cleared when the frequency change is done.
7:6RSVDRO0Reserved for future use
5:4CORE_CLK_SELRW0x0Core1 Clock Source Select:
0x0 = rcpu_sys_clk
0x1 = 614 MHz
0x2 = 491 MHz
0x3 = Reserved
3:2RSVDRO0Reserved for future use
1:0CORE_CLK_DIVRW0x0Core Clock Divider = this field + 1
RT24_CORE0_SW_RESET​

RT24_CORE0_SW_RESET Offset:0xCC

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RT24_CORE0_SW_RESETNRW0x0RT24 Core0 Software Reset Control:
0 = Reset
1 = Release Reset
RT24_CORE1_SW_RESET​

RT24_CORE1_SW_RESET Offset:0xD0

BitsFieldTypeResetDescription
31:1RSVDRO0Reserved for future use
0RT24_CORE1_SW_RESETNRW0x0RT24 Core1 Software Reset Control:
0 = Release Reset
1 = Reset

RCPU_PWMCTRL​

CLOCK/RESET CONTROL REGISTER FOR RCPU PWM​

R_PWMn_CLK_RST (n = 0~9) Offset:0x00/0x04/0x08/0x0C/0x10/0x14/0x18/0x1C/0x20/0x24

BitsFieldTypeResetDescription
31:19RSVDRO0Reserved for future use
18:8FNCLKDIVRW0x0Functional Clock Divider:
Real Divider Value = (FNCLKDIV + 1)
7:6RSVDRO0Reserved for future use
5:4FNCLKSELRW0x0Functional Clock Source Select:
0x0 = 245.76 MHz
0x1 = 24.576 MHz
All other values = Reserved
3RSVDRO0Reserved for future use
2RSTRW0x1Reset Generation Control:
Resets both APB and functional domains.
0 = Release Reset
1 = Assert Reset
1FNCLKRW0x0Functional Clock Gate Control:
0 = Disable
1 = Enable
0APBCLKRW0x0APB Bus Clock Gate Control:
0 = Disable
1 = Enable