7. Interrupt Assignments
K3 contains an Advanced Core Local Interruptor (ACLINT) and an Advanced Platform Level Interrupt Controller (APLIC).
-
ACLINT, as the local interrupt controller, includes the following functions:
- Hart local software interrupt control
- Hart local timer interrupt control
-
APLIC, as the external interrupt controller, includes the following functions:
- Support for up to 1023 external interrupts
- MSI output mode only
- Hardware-configurable interrupt delegation
- Support for interrupt modes 0, 1, and 4-76 for non-delegated interrupts
- Support for hartid up to 16383
- Configurable EIID width
7.1 Main CPU Interrupts
| Interrupt Number | Signal Name |
|---|---|
| aplic_int[1] | C0_ciu_async_abort_int |
| aplic_int[2] | C1_ciu_async_abort_int |
| aplic_int[3] | C2_ciu_async_abort_int |
| aplic_int[4] | C3_ciu_async_abort_int |
| aplic_int[5] | s_dma0_intr |
| aplic_int[6] | s_dma1_intr |
| aplic_int[7] | a_dma0_intr |
| aplic_int[8] | a_dma1_intr |
| aplic_int[9] | a_dma2_intr |
| aplic_int[10] | a_dma3_intr |
| aplic_int[11] | a_dma4_intr |
| aplic_int[12] | a_dma5_intr |
| aplic_int[13] | a_dma6_intr |
| aplic_int[14] | a_dma7_intr |
| aplic_int[15] | hsdma_iopmp_int |
| aplic_int[19] | m1_i2c8_int |
| aplic_int[20] | m1_irc1_int |
| aplic_int[21] | m1_rtc_hzclk_int_ndr |
| aplic_int[22] | m1_rtc_slp_alarm_ndr |
| aplic_int[23] | m1_timer_1_irq |
| aplic_int[24] | m1_timer_2_irq |
| aplic_int[25] | m1_timer_3_irq |
| aplic_int[26] | m1_timer1_1_irq |
| aplic_int[27] | m1_timer1_2_irq |
| aplic_int[28] | m1_timer1_3_irq |
| aplic_int[29] | m1_new_timer_1_irq |
| aplic_int[30] | m1_new_timer_2_irq |
| aplic_int[31] | m1_new_timer_3_irq |
| aplic_int[32] | m1_ndr_timer_1_irq |
| aplic_int[33] | m1_ndr_timer_2_irq |
| aplic_int[34] | m1_ndr_timer_3_irq |
| aplic_int[35] | m1_wdt_irq |
| aplic_int[36] | m1_i2c0_int |
| aplic_int[37] | m1_i2c1_int |
| aplic_int[38] | m1_i2c2_int |
| aplic_int[39] | m1_i2c3_int |
| aplic_int[40] | m1_i2c4_int |
| aplic_int[41] | m1_i2c5_int |
| aplic_int[42] | m1_ffuart0_int |
| aplic_int[43] | m1_ffuart1_int |
| aplic_int[44] | m1_ffuart2_int |
| aplic_int[45] | m1_ffuart3_int |
| aplic_int[46] | m1_ffuart4_int |
| aplic_int[47] | m1_ffuart5_int |
| aplic_int[48] | m1_ffuart6_int |
| aplic_int[49] | m1_ffuart7_int |
| aplic_int[50] | m1_ffuart8_int |
| aplic_int[51] | m1_ffuart9_int |
| aplic_int[52] | m1_ipc_adsp2ap_int_comb |
| aplic_int[53] | m1_ripc0_int0 |
| aplic_int[54] | m1_ssp2_int_req |
| aplic_int[55] | m1_ssp3_int_req |
| aplic_int[56] | m1_sspa0_int_req |
| aplic_int[57] | m1_sspa1_int_req |
| aplic_int[58] | m1_gpio_int_ap |
| aplic_int[59] | m1_gpio_int_ap_sec |
| aplic_int[60] | m1_gpio_edge_det_wakeup |
| aplic_int[61] | tsen_int |
| aplic_int[62] | m1_onewire_int |
| aplic_int[63] | m1_kp_int, m1_keypad_wakeup |
| aplic_int[64] | m1_PMIC_INT_edge_detected |
| aplic_int[65] | m1_pm_xsc_wakeup_int_mux |
| aplic_int[66] | m1_sec_rtc_hzclk_int_ndr |
| aplic_int[67] | m1_sec_rtc_slp_alarm_ndr |
| aplic_int[68] | m1_dro_int |
| aplic_int[69] | m1_irc_int |
| aplic_int[70] | m1_i2c6_int |
| aplic_int[71] | ipe4_irq |
| aplic_int[72] | dma_int_ap_non_sec |
| aplic_int[73] | dma_int_ap_sec |
| aplic_int[74] | vpu_irq |
| aplic_int[75] | gpu_irqgpu |
| aplic_int[76] | gpu_irqjob |
| aplic_int[77] | gpu_irqevent |
| aplic_int[78] | gpu_irqmmu |
| aplic_int[79] | m1_wdt_irq_match1 |
| aplic_int[80] | ccic_mmu_irq |
| aplic_int[81] | ipe_irq |
| aplic_int[82] | ipe2_irq |
| aplic_int[83] | ipe3_irq |
| aplic_int[84] | m1_sec_rtc_ms_int |
| aplic_int[85] | m1_rtc_ms_int |
| aplic_int[86] | v2d_irq |
| aplic_int[88] | dpu_cmb_secu_int |
| aplic_int[89] | dpu_offl_int |
| aplic_int[90] | dpu_cmb_int |
| aplic_int[91] | lcd_de_irq |
| aplic_int[92] | lcd_se_irq |
| aplic_int[93] | ccic_dma_irq |
| aplic_int[94] | dmmu_irq |
| aplic_int[95] | dsi_irq_a |
| aplic_int[96] | ad_irq |
| aplic_int[97] | aud_wakeup |
| aplic_int[98] | aud_wdt2_irq |
| aplic_int[99] | mmc1_int |
| aplic_int[100] | mmc2_int |
| aplic_int[101] | mmc3_int |
| aplic_int[102] | sdh2icu_wakeup_int1 |
| aplic_int[103] | sdh2icu_wakeup_int2 |
| aplic_int[104] | sdh2icu_wakeup_int3 |
| aplic_int[105] | usb2_port_int |
| aplic_int[106] | acryp_interrupt |
| aplic_int[107] | aeu_int |
| aplic_int[108] | fabric0_timeout |
| aplic_int[109] | ddr_arm_int |
| aplic_int[110] | wtm_hst_int_out |
| aplic_int[111] | wtm_sp_int_out |
| aplic_int[112] | pmu_irq2 |
| aplic_int[113] | bcm0_sp_int_out, bcm0_hst_int_out |
| aplic_int[114] | aud_wdt_irq |
| aplic_int[115] | mc_irq |
| aplic_int[116] | ddrphy_irq |
| aplic_int[117] | qspi_int |
| aplic_int[118] | usb3_porta_int |
| aplic_int[119] | alzo_status[1] |
| aplic_int[120] | arb_timeout1_int_level |
| aplic_int[121] | apb_mon_int |
| aplic_int[122] | mc_irq_scy |
| aplic_int[124] | aud_wdt_irq_m1 |
| aplic_int[125] | usb3_portb_int |
| aplic_int[126] | hook_key_int |
| aplic_int[127] | aud_plug_int |
| aplic_int[128] | sm2_pmdone_int |
| aplic_int[129] | sm2_padone_int |
| aplic_int[130] | emac2_intr |
| aplic_int[131] | emac0_intr |
| aplic_int[132] | edp0_irq |
| aplic_int[133] | emac1_intr |
| aplic_int[134] | dma_iopmp_int |
| aplic_int[135] | ufs_intr |
| aplic_int[136] | pcie_phy_int_merge |
| aplic_int[137] | dpu2_onl_secu_int |
| aplic_int[138] | dpu2_offl_int |
| aplic_int[139] | dpu2_onl_int |
| aplic_int[140] | edp1_irq |
| aplic_int[141] | pcie_a_interrupt_out |
| aplic_int[142] | pcie_b_interrupt_out |
| aplic_int[143] | pcie_c_interrupt_out |
| aplic_int[144] | ~CCI_nERRORIRQ_ap |
| aplic_int[145] | pcie_d_interrupt_out |
| aplic_int[146] | pcie_e_interrupt_out |
| aplic_int[147] | espi_event_intr |
| aplic_int[148] | usb3_portc_int |
| aplic_int[149] | usb3_portd_int |
| aplic_int[150] | dma2_int_ap_non_sec |
| aplic_int[151] | dma2_int_ap_sec |
| aplic_int[152] | espi_vw_intr |
| aplic_int[153] | espi_con_intr |
| aplic_int[154] | aud_wdt2_irq_m1 |
| aplic_int[155] | usb_vbus_id_wakeup[0] |
| aplic_int[156] | usb_vbus_id_wakeup[1] |
| aplic_int[157] | usb_vbus_id_wakeup[2] |
| aplic_int[158] | usb_vbus_id_wakeup[3] |
| aplic_int[159] | usb_vbus_id_wakeup[4] |
| aplic_int[161] | can0_int0 |
| aplic_int[162] | can0_int1 |
| aplic_int[163] | can1_int0 |
| aplic_int[164] | can1_int1 |
| aplic_int[165] | can2_int0 |
| aplic_int[166] | can2_int1 |
| aplic_int[167] | can3_int0 |
| aplic_int[168] | can3_int1 |
| aplic_int[169] | can4_int0 |
| aplic_int[170] | can4_int1 |
| aplic_int[171] | m1_timer2_1_irq |
| aplic_int[172] | m1_timer2_2_irq |
| aplic_int[173] | m1_timer2_3_irq |
| aplic_int[174] | m1_timer_wdt_irq0 |
| aplic_int[175] | m1_timer_wdt_irq1 |
| aplic_int[176] | m1_timer1_wdt_irq0 |
| aplic_int[177] | m1_timer1_wdt_irq1 |
| aplic_int[178] | m1_timer2_wdt_irq0 |
| aplic_int[179] | m1_timer2_wdt_irq1 |
| aplic_int[180] | m1_timer3_wdt_irq0 |
| aplic_int[181] | m1_timer3_wdt_irq1 |
| aplic_int[182] | m1_timer3_1_irq |
| aplic_int[183] | m1_timer3_2_irq |
| aplic_int[184] | m1_timer3_3_irq |
| aplic_int[185] | m1_timer4_1_irq |
| aplic_int[186] | m1_timer4_2_irq |
| aplic_int[187] | m1_timer4_3_irq |
| aplic_int[188] | m1_timer5_1_irq |
| aplic_int[189] | m1_timer5_2_irq |
| aplic_int[190] | m1_timer5_3_irq |
| aplic_int[191] | m1_timer6_1_irq |
| aplic_int[192] | m1_timer6_2_irq |
| aplic_int[193] | m1_timer6_3_irq |
| aplic_int[194] | m1_timer7_1_irq |
| aplic_int[195] | m1_timer7_2_irq |
| aplic_int[196] | m1_timer7_3_irq |
| aplic_int[210] | mailbox_irq0[0] |
| aplic_int[211] | mailbox_irq0[1] |
| aplic_int[212] | mailbox_irq1[0] |
| aplic_int[213] | mailbox_irq1[1] |
| aplic_int[214] | mailbox_irq2[0] |
| aplic_int[215] | mailbox_irq2[1] |
| aplic_int[216] | mailbox_irq3[0] |
| aplic_int[217] | mailbox_irq4[0] |
| aplic_int[218] | spinlock_irq |
| aplic_int[219] | pcie_a_wakeup_int |
| aplic_int[220] | pcie_b_wakeup_int |
| aplic_int[221] | pcie_c_wakeup_int |
| aplic_int[222] | pcie_d_wakeup_int |
| aplic_int[223] | pcie_e_wakeup_int |
| aplic_int[224] | riscv_iopmp_int |
| aplic_int[225] | f2m_iopmp_int |
| aplic_int[226] | mailbox_irq5[0] |
| aplic_int[227] | mailbox_irq6[0] |
| aplic_int[228] | iopmp_int0 |
| aplic_int[229] | iopmp_int1 |
| aplic_int[230] | iopmp_int2 |
| aplic_int[231] | iopmp_int3 |
| aplic_int[232] | ioatc0_int |
| aplic_int[233] | ioats_ras_int |
| aplic_int[234] | ioats_iommu_int |
| aplic_int[235] | te200_s_intr, te200_n_intr |
| aplic_int[236] | R_emac3_wkup_intr |
| aplic_int[237] | R_emac3_intr |
| aplic_int[238] | R_espi_event_intr |
| aplic_int[239] | R_espi_con_intr |
| aplic_int[240] | R_espi_vw_intr |
| aplic_int[241] | R_can0_int0 |
| aplic_int[242] | R_can0_int1 |
| aplic_int[243] | R_can1_int0 |
| aplic_int[244] | R_can1_int1 |
| aplic_int[245] | R_can2_int0 |
| aplic_int[246] | R_can2_int1 |
| aplic_int[247] | R_can3_int0 |
| aplic_int[248] | R_can3_int1 |
| aplic_int[249] | R_can4_int0 |
| aplic_int[250] | R_can4_int1 |
| aplic_int[251] | R_shub_uart_int[0] |
| aplic_int[252] | R_shub_uart_int[1] |
| aplic_int[253] | R_shub_uart_int[2] |
| aplic_int[254] | R_shub_uart_int[3] |
| aplic_int[255] | R_shub_uart_int[4] |
| aplic_int[256] | R_shub_uart_int[5] |
| aplic_int[257] | R_adma0_ch0_int |
| aplic_int[258] | R_adma0_ch1_int |
| aplic_int[259] | R_(dfe_int , sspa0_int) |
| aplic_int[260] | R_adma1_ch0_int |
| aplic_int[261] | R_adma1_ch0_int |
| aplic_int[262] | R_sspa1_int |
| aplic_int[263] | R_adma2_ch0_int |
| aplic_int[264] | R_adma2_ch1_int |
| aplic_int[265] | R_sspa2_int |
| aplic_int[266] | R_adma3_ch0_int |
| aplic_int[267] | R_adma3_ch0_int |
| aplic_int[268] | (sspa3_int , dmac_int) |
| aplic_int[269] | R_shubssp_int_req[0] |
| aplic_int[270] | R_shubssp_int_req[1] |
| aplic_int[271] | R_shubssp_int_req[2] |
| aplic_int[272] | R_shub_i2c_int_i[0] |
| aplic_int[273] | R_shub_i2c_int_i[1] |
| aplic_int[274] | R_irc_int |
| aplic_int[275] | R_irc1_int |
| aplic_int[276] | emac0_wkup_intr |
| aplic_int[277] | emac1_wkup_intr |
| aplic_int[278] | emac2_wkup_intr |
| aplic_int[279] | ioatc1_int |
| aplic_int[280] | ioatc2_int |
| aplic_int[281] | m1_ffuart10_int |
| aplic_int[282] | m1_ssp1_int_req |
| aplic_int[283] | m1_ssp0_int_req |
| aplic_int[284] | m1_sspa3_int_req |
| aplic_int[285] | m1_sspa2_int_req |
| aplic_int[286] | m1_sspa5_int_req |
| aplic_int[287] | m1_sspa4_int_req |
| aplic_int[288] | ddrc0_PhyInt_fault[0] |
| aplic_int[289] | ddrc0_PhyInt_fault[1] |
| aplic_int[290] | ddrc0_PhyInt_fault[2] |
| aplic_int[291] | ddrc0_PhyInt_fault[3] |
| aplic_int[292] | ddrc0_PhyInt_fault[4] |
| aplic_int[293] | ddrc0_PhyInt_fault[5] |
| aplic_int[294] | ddrc1_PhyInt_fault[0] |
| aplic_int[295] | ddrc1_PhyInt_fault[1] |
| aplic_int[296] | ddrc1_PhyInt_fault[2] |
| aplic_int[297] | ddrc1_PhyInt_fault[3] |
| aplic_int[298] | ddrc1_PhyInt_fault[4] |
| aplic_int[299] | ddrc1_PhyInt_fault[5] |
| aplic_int[300] | ddrc0_PhyInt_n[0] |
| aplic_int[301] | ddrc0_PhyInt_n[1] |
| aplic_int[302] | ddrc0_PhyInt_n[2] |
| aplic_int[303] | ddrc0_PhyInt_n[3] |
| aplic_int[304] | ddrc0_PhyInt_n[4] |
| aplic_int[305] | ddrc0_PhyInt_n[5] |
| aplic_int[306] | ddrc0_PhyInt_n[6] |
| aplic_int[307] | ddrc1_PhyInt_n[0] |
| aplic_int[308] | ddrc1_PhyInt_n[1] |
| aplic_int[309] | ddrc1_PhyInt_n[2] |
| aplic_int[310] | ddrc1_PhyInt_n[3] |
| aplic_int[311] | ddrc1_PhyInt_n[4] |
| aplic_int[312] | ddrc1_PhyInt_n[5] |
| aplic_int[313] | ddrc1_PhyInt_n[6] |
| aplic_int[314] | derate_temp_limit_intr_ddrc0 |
| aplic_int[315] | derate_temp_limit_intr_ddrc1 |
7.2 Real-Time CPU Interrupts
| Interrupt Number | Signal Name |
|---|---|
| int_src[1] | unmsk_lp_int[3] |
| int_src[2] | aud_ap_force_pwr_on_irq |
| int_src[3] | irc1_int |
| int_src[4] | rsm_irq |
| int_src[5] | adma0_ch0_int |
| int_src[6] | adma0_ch1_int |
| int_src[7] | (dfe_int , sspa0_int) |
| int_src[8] | timer_1_irq |
| int_src[9] | timer_2_irq |
| int_src[10] | timer_3_irq |
| int_src[11] | ipc_ap2aud_int |
| int_src[12] | ipc_cp2aud_int |
| int_src[13] | shub_i2c_int_i[0] |
| int_src[14] | shub_i2c_int_i[1] |
| int_src[15] | shubssp_int_req[0] |
| int_src[16] | shubssp_int_req[1] |
| int_src[17] | shub_uart_int[0] |
| int_src[18] | shub_uart_int[1] |
| int_src[19] | shub_uart_int[2] |
| int_src[20] | shub_uart_int[3] |
| int_src[21] | shub_uart_int[4] |
| int_src[22] | aud_ap_wakeup |
| int_src[23] | sensor_hub_ripc_int |
| int_src[24] | sensor_hub_int[0] |
| int_src[25] | sensor_hub_int[1] |
| int_src[26] | sensor_hub_int[2] |
| int_src[27] | sensor_hub_int[3] |
| int_src[28] | sensor_hub_int[4] |
| int_src[29] | sensor_hub_int[5] |
| int_src[30] | sensor_hub_int[6] |
| int_src[31] | sensor_hub_int[7] |
| int_src[32] | dmac_int |
| int_src[33] | adma1_ch1_int |
| int_src[34] | adma1_ch0_int |
| int_src[35] | sspa1_int |
| int_src[36] | can0_int0 |
| int_src[37] | can0_int1 |
| int_src[38] | adma2_ch1_int |
| int_src[39] | adma2_ch0_int |
| int_src[40] | sspa2_int |
| int_src[41] | can1_int0 |
| int_src[42] | can1_int1 |
| int_src[43] | irc_int |
| int_src[44] | shub_uart_int[5] |
| int_src[45] | shub_edge_det_int |
| int_src[46] | timer2_1_irq |
| int_src[47] | timer2_2_irq |
| int_src[48] | timer2_3_irq |
| int_src[49] | aud_gpio_int_ap |
| int_src[50] | aud_gpio_edge_int |
| int_src[51] | adma3_ch1_int |
| int_src[52] | adma3_ch0_int |
| int_src[53] | shubssp_int_req[2] |
| int_src[54] | espi_event_intr |
| int_src[55] | espi_con_intr |
| int_src[56] | espi_vw_intr |
| int_src[57] | emac3_intr |
| int_src[58] | can2_int0 |
| int_src[59] | can2_int1 |
| int_src[60] | can3_int0 |
| int_src[61] | can3_int1 |
| int_src[62] | can4_int0 |
| int_src[63] | can4_int1 |
| int_src[64] | emac3_wkup_intr |
| int_src[65] | mailbox_irq0[0] |
| int_src[66] | mailbox_irq0[1] |
| int_src[67] | ap_spinlock_irq |
| int_src[68] | ap_mailbox_irq3_1 |
| int_src[69] | ap_mailbox_irq4_1 |
| int_src[70] | ap_mailbox_irq5_1 |
| int_src[71] | ap_mailbox_irq6_1 |
| int_src[72] | aud_wdt_irq_m1 |
| int_src[73] | aud_wdt_irq |
| int_src[74] | aud_wdt2_irq_m1 |
| int_src[75] | aud_wdt2_irq |
| int_src[76] | timer3_1_irq |
| int_src[77] | timer3_2_irq |
| int_src[78] | timer3_3_irq |
| int_src[79] | timer4_1_irq |
| int_src[80] | timer4_2_irq |
| int_src[81] | timer4_3_irq |
| int_src[82] | shub_i2c_int_i[2] |
| int_src[83] | ap_c0_m2_enter_int |
| int_src[84] | ap_c0_m2_wakeup_int |
| int_src[85] | ap_c1_m2_enter_int |
| int_src[86] | ap_c1_m2_wakeup_int |
| int_src[87] | ap_c2_m2_enter_int |
| int_src[88] | ap_c2_m2_wakeup_int |
| int_src[89] | ap_c3_m2_enter_int |
| int_src[90] | ap_c3_m2_wakeup_int |
| int_src[91] | soc_d12_int |
| int_src[92] | d2_wakeup_int |
| int_src[93] | acpu_irq[0] (GPIO) |
| int_src[94] | acpu_irq[1] (GPIO edge) |
| int_src[95] | acpu_irq[2] (tsensor) |
| int_src[103] | f2m_iopmp_int |
| int_src[104] | riscv_iopmp_int |
| int_src[105] | iopmp_int0 |
| int_src[106] | iopmp_int1 |
| int_src[107] | iopmp_int2 |
| int_src[108] | iopmp_int3 |
| int_src[109] | dma_iopmp_int |
| int_src[110] | to_rcpu_abort_int[0] |
| int_src[111] | to_rcpu_abort_int[1] |
| int_src[112] | to_rcpu_abort_int[2] |
| int_src[113] | to_rcpu_abort_int[3] |
| int_src[114] | m2f_iopmp_int |